Los Angeles, CA
June 5, 2000 to June 9, 2000
William R. Lee , System Level Design Methodology Leader, IBM, ASICs, NC
Amit Goel , Hamerschlag Hall, Pittsburgh, PA
This paper describes the model checking effort for an arbiter core for the IBM CoreConnect Architecture. We present our verification methodology and describe how it was influenced by the architecture. We also present and analyze the bugs found and discuss the difficulties associated with verifying complex on-chip buses, highlighting the need for better tools and methodologies for their specification and verification.
fault modeling, fault simulation, hard faults, test vector generation
William R. Lee, Amit Goel, "Formal Verification of an IBM CoreConnect Processor Local bus Arbiter Core", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 196-200, doi:10.1109/DAC.2000.855303