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37th Conference on Design Automation (DAC'00)
A Realizable Driving Point Model for on-Chip Interconnect with Inductance
Los Angeles, CA
June 05-June 09
ISBN: 1-58113-1897-9
Byron L. Krauter, IBM Corporation, Austin, TX
Chandramouli V. Kashyap, IBM Corporation, Austin, TX
In this paper we present a generalization of popular linear model reduction methods, such as Lanczos- and Arnoldi-based algorithms based on rational approximation, to systems whose response to interesting external inputs can be described by a few terms in a functional series expansion such as a Volterra series. The approach allows automatic generation of macromodels that include frequency-dependent nonlinear effects.
Index Terms:
fault modeling, fault simulation, hard faults, test vector generation
Citation:
Byron L. Krauter, Chandramouli V. Kashyap, "A Realizable Driving Point Model for on-Chip Interconnect with Inductance," dac, pp.190-195, 37th Conference on Design Automation (DAC'00), 2000
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