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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 190-195
Byron L. Krauter , IBM Corporation, Austin, TX
Chandramouli V. Kashyap , IBM Corporation, Austin, TX
ABSTRACT
In this paper we present a generalization of popular linear model reduction methods, such as Lanczos- and Arnoldi-based algorithms based on rational approximation, to systems whose response to interesting external inputs can be described by a few terms in a functional series expansion such as a Volterra series. The approach allows automatic generation of macromodels that include frequency-dependent nonlinear effects.
INDEX TERMS
fault modeling, fault simulation, hard faults, test vector generation
CITATION
Byron L. Krauter, Chandramouli V. Kashyap, "A Realizable Driving Point Model for on-Chip Interconnect with Inductance", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 190-195, doi:10.1109/DAC.2000.855302
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