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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 172-175
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, MA
Rakesh Vallishayee , PDF Solutions, San Jose, CA
Sani Nassif , IBM, Austin, TX
Shiou Lin Sam , Massachusetts Institute of Technology, Cambridge, MA
Duane Boning , Massachusetts Institute of Technology, Cambridge, MA
Vikas Mehrotra , Massachusetts Institute of Technology, Cambridge, MA
We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect delay and clock skew in both aluminum and copper interconnect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD variation has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations.
fault modeling, fault simulation, hard faults, test vector generation
Anantha Chandrakasan, Rakesh Vallishayee, Sani Nassif, Shiou Lin Sam, Duane Boning, Vikas Mehrotra, "A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 172-175, doi:10.1109/DAC.2000.855298
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