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Los Angeles, CA
June 5, 2000 to June 9, 2000
ISBN: 1-58113-1897-9
pp: 168-171
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh, PA
Sani R. Nassif , IBM Austin Research Lab, Austin, TX
Ying Liu , Carnegie Mellon University, Pittsburgh, PA
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.
fault modeling, fault simulation, hard faults, test vector generation
Lawrence T. Pileggi, Andrzej J. Strojwas, Sani R. Nassif, Ying Liu, "Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor", DAC, 2000, Design Automation Conference, Design Automation Conference 2000, pp. 168-171, doi:10.1109/DAC.2000.855297
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