This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
37th Conference on Design Automation (DAC'00)
Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor
Los Angeles, CA
June 05-June 09
ISBN: 1-58113-1897-9
Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA
Andrzej J. Strojwas, Carnegie Mellon University, Pittsburgh, PA
Sani R. Nassif, IBM Austin Research Lab, Austin, TX
Ying Liu, Carnegie Mellon University, Pittsburgh, PA
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.
Index Terms:
fault modeling, fault simulation, hard faults, test vector generation
Citation:
Lawrence T. Pileggi, Andrzej J. Strojwas, Sani R. Nassif, Ying Liu, "Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor," dac, pp.168-171, 37th Conference on Design Automation (DAC'00), 2000
Usage of this product signifies your acceptance of the Terms of Use.