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Design Automation Conference (1998)
San Francisco, California
June 15, 1998 to June 19, 1998
ISBN: 0-89791-964-5
TABLE OF CONTENTS
Reviewers (PDF)
pp. xii
Executive Plenary Panel
Session 1: Interfaces for Design Reuse
Jordi Cortadella , Technical University of Catalonia, Barcelona, Spain
Alex Kondratyev , The University of Aizu, Aizu-Wakamatsu, Japan
pp. 2-7
James A. Rowson , Alta Group of Cadence, Sunnyvale, California
Alberto Sangiovanni-Vincentelli , University of California at Berkeley
pp. 8-13
Giovanni De Micheli , Stanford University, CA
pp. 14-19
Session 2: Analog and Mixed-Signal Design Tools
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
Mike Chou , Massachusetts Institute of Technology, Cambridge, MA
pp. 20-25
Amit Mehrotra , Bell Laboratories, Murray Hill, New Jersey
Jaijeet Roychowdhury , Bell Laboratories, Murray Hill, New Jersey
pp. 26-31
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul
pp. 32-37
U. Choudhury , Cadence Design Systems, San Jose, CA
W. H. Kao , Cadence Design Systems, San Jose, CA
E. Charbon , Cadence Design Systems, San Jose, CA
E. Malavasi , Cadence Design Systems, San Jose, CA
B. G. Arsintescu , Delft University of Technology, The Netherlands
pp. 38-43
Session 3: University Design Contest
Ahmadreza Rofougaran , UCLA Electrical Engineering, Los Angeles, CA
Jacob Rael , UCLA Electrical Engineering, Los Angeles, CA
pp. 44-49
Klaus Herrmann , Universit?t Hannover, Germany
Peter Pirsch , Universit?t Hannover, Germany
Dirk Niggemeyer , Universit?t Hannover, Germany
J? Hilgenstock , Universit?t Hannover, Germany
pp. 50-55
Helge Kloos , Universit?t Hannover, Germany
Johannes Kneip , Universit?t Hannover, Germany
Martin Ohmacht , Universit?t Hannover, Germany
Hanno Lieske , Universit?t Hannover, Germany
Peter Pirsch , Universit?t Hannover, Germany
Willm Hinrichs , Universit?t Hannover, Germany
Jens Peter Wittenburg , Universit?t Hannover, Germany
pp. 56-61
Jan M. Rabaey , University of California, Berkeley
Roy A. Sutton , University of California, Berkeley
pp. 62-65
K. Loveless , University of Toronto, Canada
M. Stumm , University of Toronto, Canada
N. Manjikian , Queen's University at Kingston, Canada
R. Grindley , University of Toronto, Canada
S. Brown , University of Toronto, Canada
S. Caranci , University of Toronto, Canada
S. Srbljic , University of Zagreb, Croatia
Z. Vranesic , University of Toronto, Canada
Z. Zilic , Lucent Technologies, Allentown, PA
G. Lemieux , University of Toronto, Canada
A. Grbic , University of Toronto, Canada
pp. 66-69
Session 4: Embedded System Design and Exploration
Josh MacDonald , University of California, Berkeley
Michael Shilman , University of California, Berkeley
Paul Hilfinger , University of California, Berkeley
A. Richard Newton , University of California, Berkeley
Abdallah Tabbara , University of California, Berkeley
pp. 70-75
Kris Croes , IMEC, Leuven, Belgium
Miguel Miranda , IMEC, Leuven, Belgium
Paul Six , IMEC, Leuven, Belgium
Sven Wuytack , IMEC, Leuven, Belgium
Chantal Ykman-Couvreur , IMEC, Leuven, Belgium
Diederik Verkest , IMEC, Leuven, Belgium
Francky Catthoor , IMEC, Leuven, Belgium
Gjalt de Jong , Alcatel, Antwerp, Belgium
Julio Leao da Silva , IMEC, Leuven, Belgium
pp. 76-81
Henk Corporaal , Delft University of Technology, The Netherlands
pp. 82-87
Session 5: Taming Noise in Deep-Submicron Digital Designs
Kenneth L. Shepard , Columbia University, New York, NY
pp. 94-99
Session 6: Control and Data Driven High Level Synthesis
Niraj K. Jha , Department of Electrical Engineering, Princeton, NJ
Ganesh Lakshminarayana , Department of Electrical Engineering, Princeton, NJ
pp. 102-107
Anand Raghunathan , NEC USA, Princeton, NJ
Niraj K. Jha , Princeton University, Princeton, NJ
Ganesh Lakshminarayana , Princeton University, Princeton, NJ
pp. 108-113
Miriam Leeser , Northeastern University, Boston, MA
Shantanu Tarafdar , Northeastern University, Boston, MA
pp. 114
Moonwook Oh , Seoul National University, Seoul, Korea
Soonhoi Ha , Seoul National University, Seoul, Korea
pp. 118
Session 7: Synthesis Flow in Deep Submicron Technologies
Robert K. Brayton , University of California at Berkeley, California
pp. 122-127
Jinan Lou , University of Southern California, Los Angeles, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
Amir H. Salek , University of Southern California, Los Angeles, CA
pp. 128-134
Session 8: Environment for Collaborative Design
Stephen W. Director , University of Michigan, Ann Arbor
Peter R. Sutton , Queensland University of Technology, Australia
pp. 134-139
Mark D. Spiller , University of California at Berkeley
Francis L. Chan , University of California at Berkeley
pp. 146-151
Session 9: New Methods in Functional Verification
Michael Orgad , IBM Research Lab in Haifa, Israel
Avi Ziv , IBM Research Lab in Haifa, Israel
Shmuel Ur , IBM Research Lab in Haifa, Israel
Eran Harel , IBM Research Lab in Haifa, Israel
Raanan Grinwald , IBM Research Lab in Haifa, Israel
pp. 158-163
Hoon Choi , KAIST, Taejon, Korea
In-Cheolo Park , KAIST, Taejon, Korea
Seungjong Lee , KAIST, Taejon, Korea
Seungwang Lee , KAIST, Taejon, Korea
Chong-Min Kyung , KAIST, Taejon, Korea
Namseung Kim , KAIST, Taejon, Korea
pp. 170-173
Session 10: Panel
Session 11: System-Level Power Optimization
Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
Gang Qu , University of California, Los Angeles
Inki Hong , University of California, Los Angeles
pp. 176-181
L. Benini , Stanford University, CA
A. Bogliolo , Universit? di Bologna, Italy
G. De Micheli , Stanford University, CA
G. A. Paleologo , Stanford University, CA
pp. 182-187
J? Henkel , NEC USA, Princeton, NJ
Yanbing Li , Princeton University, NJ
pp. 188-193
Session 12: Boolean Methods
Nicole Drechsler , Albert-Ludwigs-University, Germany
Rolf Drechsler , Albert-Ludwigs-University, Germany
pp. 200-205
Reiner Kolla , Universit?t W?rzburg, Germany
Uwe Hinsberger , HighTec EDV-Systeme GmbH, Germany
pp. 206-211
Session 13: Extraction and Modeling for Interconnect
Naveen Kakani , Univ. of North Texas, Denton, TX
Tiejun Yu , Univ. of North Carolina, Charlotte, NC
Jianguo Liu , Univ. of North Texas, Denton, TX
pp. 212-217
Ronald A. Rohrer , Intersouth Partners, RTP, NC
E. Aykut Dengi , Motorola Inc., Austin, TX
pp. 218-223
Wayne W. M. Dai , UC Santa Cruz, CA
David E. Long , Lucent Technologies, Murray Hill, NJ
Sharad Kapur , Lucent Technologies, Murray Hill, NJ
pp. 224-229
Session 14: Processor Design and Simulation
Madhav P. Desai , Indian Institute of Technology, Mumbai, India
Dale H. Hall , Digital Equipment Corportation, Hudson MA
Nevine Nassif , Digital Equipment Corportation, Hudson MA
pp. 230-235
Robert H. Klenke , University of Virginia, Charlottesville
Robert McGraw , RAM Laboratories, Encinitas, CA
pp. 236-241
Mary Jane Irwin , The Pennsylvania State University
Robert M. Owens , The Pennsylvania State University
Rita Yu Chen , The Pennsylvania State University
pp. 242-245
Mitsuho Seki , Hitachi, Ltd., Japan
Ryuichi Satomura , Hitachi, Ltd., Japan
Susumu Narita , Hitachi, Ltd., Japan
Tsuyoshi Takahashi , Hitachi, Ltd., Japan
Yusuke Nitta , Hitachi, Ltd., Japan
Toshihiro Hattori , Hitachi, Ltd., Japan
pp. 246-249
Session 15: Panel
Session 16: Performance Modeling and Characterization for Embedded Systems
J.-H. Guo , University of Texas at Austin
M. Jacome , University of Texas at Austin
G. de Veciana , University of Texas at Austin
pp. 251-256
Dinesh Ramanathan , Synopsys, Inc., Mountain View, CA
Ali Dasdan , University of Illinois, Urbana
pp. 263-268
Session 17: Advances in Placement and Partitioning
Frank M. Johannes , Technical University Munich, Germany
pp. 269-274
Richard B. Brown , University Of Michigan, Ann Arbor
Phiroze N. Parakh , University Of Michigan, Ann Arbor
pp. 275-278
Majid Sarrafzadeh , Northwestern University, Evanston, IL
Maogang Wang , Northwestern University, Evanston, IL
pp. 279-282
Massoud Pedram , University of Southern California, Los Angeles, CA
pp. 287-290
Session 18: Parasitic Device Extraction and Interconnect Modeling
Sung-Mo Kang , Univ. of Illinois at Urbana-Champaign
Tong Li , Univ. of Illinois at Urbana-Champaign
pp. 291-296
L. Miguel Silveira , INESC/Cadence European Laboratories, Lisboa, Portugal
Jacob White , Massachusetts Institute of Technology, Cambridge, MA
Nuno Marques , INESC/Cadence European Laboratories, Lisboa, Portugal
pp. 297-302
Session 19: Design Optimization for DSP
Miodrag Potkonjak , University of California, Los Angeles, CA
Jan Rabaey , University of California, Berkeley, CA
pp. 309-314
Luc Rijnders , IMEC vzw, Leuven
Ivo Bolsens , IMEC vzw, Leuven
Serge Vernalde , IMEC vzw, Leuven
Patrick Schaumont , IMEC vzw, Leuven
pp. 315-320
Miodrag Potkonjak , Computer Science Department, UCLA
Johnson Kin , Electrical Engineering Department, UCLA
Chunho Lee , Computer Science Department, UCLA
pp. 321-326
Session 20: Panel
Session 21: Bridging the Gap Between Simulation and Formal Verification
Session 22: Logic Optimization
Chang Wu , University of California, Los Angeles, CA
pp. 330-335
Karem A. Sakallah , University of Michigan, Ann Arbor
pp. 336-341
David Ihsin Cheng , Ultima Interconnect Tech., Sunnyvale, CA
Shih-Chieh Chang , Nationa Chung Cheng University, Taiwan
pp. 342-347
Robert K. Brayton , University of California, Berkeley
Prashant Sawkar , Intel Corporation, Hillsboro, OR
pp. 348-351
David S. Kung , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 352-355
Session 23: Routing for Performance and Crosstalk
Patrick H. Madden , UCLA Computer Science Department, Los Angeles, California
Jason Cong , UCLA Computer Science Department, Los Angeles, California
pp. 356-361
Anirudh Devgan , IBM Austin Research Laboratory, Austin, TX
Charles J. Alpert , IBM Austin Research Laboratory, Austin, TX
pp. 362-367
Premal Buch , Magma Design Automation, Palo Alto, CA
John Lillis , Magma Design Automation, Palo Alto, CA
pp. 368-373
D. F. Wong , University of Texas, Austin, TX
Hai Zhou , University of Texas, Austin, TX
pp. 374-377
Louis Scheffer , Cadence Design Systems, Inc., San Jose, CA
Carl Sechen , University of Washington, Seattle
Hsiao-Ping Tseng , University of Washington, Seattle
pp. 378-381
Session 24: Practical Optimization Methodologies for High Performance Design
Jay Brockman , University of Notre Dame, IN
pp. 382-387
Joe Norton , Advanced System Technologies Lab., Motorola, Austin, TX
Tim Edwards , Advanced System Technologies Lab., Motorola, Austin, TX
Abhijit Dharchoudhury , Advanced System Technologies Lab., Motorola, Austin, TX
Rajendran Panda , Advanced System Technologies Lab., Motorola, Austin, TX
pp. 388-391
Chaim Amir , Sun Microsystems, Inc., Palo Alto, CA
John MacDonald , Sun Microsystems, Inc., Palo Alto, CA
pp. 392-395
Alexander Grie?ing , Siemens AG, M?nchen, Germany
Paolo Ienne , Siemens AG, M?nchen, Germany
pp. 396-401
Chenming Hu , University of California at Berkeley
Michael Orshansky , University of California at Berkeley
pp. 402-407
Session 25: RF IC Design Methodology
Behzad Razavi , University of California, Los Angeles
pp. 408-413
Alper Demir , Bell Laboratories, Murray Hill, NJ
Peter Feldmann , Bell Laboratories, Murray Hill, NJ
Robert Melville , Bell Laboratories, Murray Hill, NJ
Sharad Kapur , Bell Laboratories, Murray Hill, NJ
David Long , Bell Laboratories, Murray Hill, NJ
Jaijeet Roychowdhury , Bell Laboratories, Murray Hill, NJ
pp. 414-420
Session 26: Theory and Practice in High Level Synthesis
Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
pp. 427-432
William Jao , Aimfast Corp., Sunnyvale, CA
Steve Tjiang , Synopsys Inc., Mountain View, CA
pp. 433-438
Session 27: BDD Approximation Techniques
Thomas R. Shiple , Synopsys
Fabio Somenzi , University of Colorado
Kenneth L. McMillan , Cadence Design Systems
pp. 445-450
Alan J. Hu , University of British Columbia, Vancouver, Canada
Mark A. Horowitz , Stanford University, CA
David L. Dill , Stanford University, CA
Shankar G. Govindaraju , Stanford University, CA
pp. 451-456
Gary D. Hachtel , University of Colorado, Boulder
Abelardo Pardo , Mentor Graphics Corporation, Billerica, MA
pp. 457-462
Session 28: Interconnect Modeling and Timing Simulation
Lawrence Pileggi , Carnegie Mellon University
pp. 463-468
Lawrence T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Ying Liu , Carnegie Mellon University, Pittsburgh, PA
pp. 469-472
Chung-Kuan Cheng , University of California, San Diego
Fang-Jou Liu , University of California, San Diego
pp. 473-476
Ognen J. Nastov , MIT, Cambridge, MA
Tuyan V. Nguyen , IBM Austin Research Laboratory, Austin, TX
pp. 477-482
Session 29: Low Power Design Using Multiple Thresholds and Supplies
Masafumi Takahashi , Toshiba Corporation, Japan
Masahiro Kanazawa , Toshiba Corporation, Japan
Mototsugu Hamada , Toshiba Corporation, Japan
Mutsunori Igarashi , Toshiba Corporation, Japan
Tadahiro Kuroda , Toshiba Corporation, Japan
Takashi Ishikawa , Toshiba Corporation, Japan
Toshihiro Terazawa , Toshiba Corporation, Japan
Kimiyoshi Usami , Toshiba Corporation, Japan
pp. 483-488
Mark Johnson , Purdue University, W. Lafayette, IN
Vivek De , Intel Corp., Hillsboro, OR
Kaushik Roy , Purdue University, W. Lafayette, IN
Liqiong Wei , Purdue University, W. Lafayette, IN
pp. 489-494
Anantha Chandrakasan , Massachusetts Institute of Technology
James Kao , Massachusetts Institute of Technology
pp. 495-500
Session 30: Panel
Session 31: Software Synthesis and Retargetable Compilation
Bill Lin , University of California, San Diego
pp. 502-505
Peter A. Beerel , University of Southern California, Los Angeles, CA
Ellen M. Sentovich , Cadence Berkeley Laboratories, Berkeley, CA
Luciano Lavagno , Cadence Berkeley Laboratories, Berkeley, CA
pp. 506-509
Wayne Wolf , Princeton University
pp. 516-521
Session 32: Formal Methods in Functional Verification
Jeremy R. Levitt , 0-in Design Automation
David L. Dill , Stanford University, CA
Clark W. Barrett , Stanford University, CA
pp. 522-527
Kurt Keutzer , University of California, Berkeley
Farzan Fallah , MIT, Cambridge
pp. 528-533
Robert B. Jones , Intel Corporation, Hillsboro, OR
Mark D. Aagaard , Intel Corporation, Hillsboro, OR
pp. 538-541
Session 33: Core Test and BIST
Sujit Dey , University of California, San Diego
Niraj K. Jha , Princeton University, NJ
pp. 542-547
Melvin A. Breuer , University of Southern California, Los Angeles
Ishwar Parulkar , Sun Microsystems, Sunnyvale, CA
pp. 548-553
Sudipta Bhawmik , Lucent Technologies, Princeton, NJ
Indradeep Ghosh , Princeton University, NJ
pp. 554-559
Session 34: Interconnect Analysis and Reliability in Deep Sub-Micron
Eby G. Friedman , University of Rochester, New York
Yehea I. Ismail , University of Rochester, New York
pp. 560-565
Jacob White , Mass. Institute of Tech., Cambridge, MA
Steve Majors , Motorola Inc., Austin, TX
Tareq Bustami , Motorola Inc., Austin, TX
Yehia Massoud , Mass. Institute of Tech., Cambridge, MA
pp. 566-571
Haldun Haznedar , Texas Instruments, Inc., Houston, TX
Duane Young , Texas Instruments, Inc., Houston, TX
Frank Cano , Texas Instruments, Inc., Houston, TX
NS Nagaraj , Texas Instruments, Inc., Dallas, TX
pp. 572-577
Session 35: Panel
Session 36: Timing Analysis
Robert K. Brayton , University of California, Berkeley
pp. 580-585
Gaetano Borriello , University of Washington, Seattle
Tod Amon , Southwest Texas State University, San Macros, TX
pp. 586-590
Farid N. Najm , University of Illinois at Urbana-Champaign
Mahadevamurty Nemani , University of Illinois at Urbana-Champaign
pp. 591-594
Lawrence T. Pileggi , Carnegie Mellon University
pp. 595-598
Session 37: New Techniques in State Space Explorations
David L. Dill , Stanford University, CA
C. Han Yang , Stanford University, CA
pp. 599-604
Peter A. Beerel , University of Southern California, Los Angeles
Aiguo Xie , University of Southern California, Los Angeles
pp. 605-610
Jim Kukula , Synopsys, Inc.
Tom Shiple , Synopsys, Inc.
Adnan Aziz , Univ. of Texas at Austin
pp. 615-618
Session 38: Advanced ATPG Techniques
Wanli Jiang , University of Minnesota, Minneapolis
Bapiraju Vinnakota , University of Minnesota, Minneapolis
pp. 619-624
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Mark Kassab , Mentor Graphics Corporation, Wilsonville, OR
Aiman El-Maleh , Mentor Graphics Corporation, Wilsonville, OR
pp. 625-631
Kuang-Chien Chen , Verplex Systems Inc., Santa Clara, CA
Kwang-Ting Cheng , Univ. of California, Santa Barbara
Juin-Yeu Joseph Lu , National Semiconductor Corp., Santa Clara, CA
pp. 632-637
Session 39: Practical Experiences of Functional Verification for Complex ICs
Michael Quinn , Digital Equipment Corporation
Nathan Dohm , Digital Equipment Corporation
Scot Hildebrandt , Digital Equipment Corporation
Carl Ramey , Digital Equipment Corporation
Darren Brown , Digital Equipment Corporation
Scott Taylor , Digital Equipment Corporation
pp. 638-643
Avi Ziv , IBM Research Lab in Haifa, Israel
Yossi Malka , IBM Research Lab in Haifa, Israel
pp. 644-649
Allan Silburt , Nortel, Canada
Mario Dufresne , Nortel, Canada
Thane Brown , Nortel, Canada
Tung Ho , Nortel, Canada
Ying Liu , Nortel, Canada
Gary Vrckovnik , Nortel, Canada
Geoffrey Hall , Nortel, Canada
Adrian Evans , Nortel, Canada
pp. 650-655
Session 40: Panel
Session 41: Fast Functional Simulation
Mark Heinrich , Stanford University, CA
Kunle Olukotun , Stanford University, CA
pp. 658-663
Adnan Aziz , University of Texas-Austin, TX
Tjahjadi Wongsonegoro , University of Texas-Austin, TX
Yufeng Luo , Synopsys, Inc., Mountain View, CA
pp. 664-667
Michael Bershteyn , Quickturn Design Systems, Inc., San Jose, CA
Paul Vyedin , Quickturn Design Systems, Inc., San Jose, CA
Jerry Bauer , Quickturn Design Systems, Inc., San Jose, CA
pp. 668-671
Session 42: Power Estimation and Modeling
Prithviraj Banerjee , Northwestern University, Evanston, Illinois
pp. 672-677
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 678-683
Qing Wu , University of Southern California, Los Angeles, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
pp. 684-689
Eun Sei Park , Hanyang University, Ansan, Korea
Byunggyu Kwak , Samsung Data Systems, Seoul, Korea
pp. 690-693
Masahiro Fujita , Fujitsu Laboratories of America, Inc.
Rajeev Murgai , Fujitsu Laboratories of America, Inc.
pp. 694-697
Session 43: Technology Mapping for Programmable Logic
Stephen Dean Brown , University of Toronto, Canada
Jason Helge Anderson , University of Toronto, Canada
pp. 698-703
Songjie Xu , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 704-707
K. K. Lee , The University of Texas at Austin
D. F. Wong , The University of Texas at Austin
pp. 708
Jie-Hong R. Jiang , National Chiao Tung University
Juinn-Dar Huang , National Chiao Tung University
pp. 712
Luca Benini , Universit? di Bologna, Italy
Balakrishna Kumthekar , University of Colorado, Boulder
Fabio Somenzi , University of Colorado, Boulder
pp. 718
Jan-Min Hwang , Tsing Hua University, Taiwan
TingTing Hwang , Tsing Hua University, Taiwan
pp. 722
Session 44: Power Dissipation and Distribution in High Performance Processors
Daniel B. Jackson , Digital Equipment Corporation, Hudson, Massachusetts
Michael K. Gowan , Digital Equipment Corporation, Hudson, Massachusetts
pp. 726-731
Suresh Rajgopal , Intel Corporation, Santa Clara, CA
Deo Singh , Intel Corporation, Santa Clara, CA
Franklin Baez , Intel Corporation, Santa Clara, CA
Gaurav Mehta , Intel Corporation, Santa Clara, CA
Vivek Tiwari , Intel Corporation, Santa Clara, CA
pp. 732-737
Ravi Vaidyanathan , Advanced System Technologies Lab, Motorola, Austin, TX
Bogdan Tutuianu , Somerset Design Center, Austin, TX
David Bearden , Somerset Design Center, Austin, TX
David Blaauw , Advanced System Technologies Lab, Motorola, Austin, TX
Abhijit Dharchoudhury , Advanced System Technologies Lab, Motorola, Austin, TX
pp. 738-743
Syed Zakir Hussain , Simplex Solutions, Inc.
Steffen Rochel , Simplex Solutions, Inc.
Gregory Steele , Simplex Solutions, Inc.
pp. 744-749
Session 45: Challenge in the Test on System-On-A-Chip Era
Yervant Zorian , LogicVision, Inc., San Jose, California
pp. 752-757
Session 46: Controller Decomposition for Power and Area Minimization
Arlindo L. Oliveira , Cadence European Labs/IST-INESC, Portugal
pp. 758-763
A. Lioy , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
G. De Micheli , Stanford University, CA
G. Odasso , Politecnico di Torino, Italy
M. Poncino , Politecnico di Torino, Italy
pp. 764-769
Session 47: IP Protection Technologies
H. Wang , UCLA Computer Science Dept., Los Angeles, CA
I. L. Markov , UCLA Computer Science Dept., Los Angeles, CA
J. Lach , UCLA Electrical Engineering Dept., Los Angeles, CA
M. Potkonjak , UCLA Computer Science Dept., Los Angeles, CA
P. Tucker , UCSD Computer Science & Engineering Dept., La Jolla, CA
S. Mantik , UCLA Computer Science Dept., Los Angeles, CA
W. H. Mangione-Smith , UCLA Electrical Engineering Dept., Los Angeles, CA
G. Wolfe , UCLA Computer Science Dept., Los Angeles, CA
A. B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 776-781
Huijuan Wang , UCLA Computer Science Dept., Los Angeles, CA
Igor L. Markov , UCLA Computer Science Dept., Los Angeles, CA
Miodrag Potkonjak , UCLA Computer Science Dept., Los Angeles, CA
Paul Tucker , UCSD Computer Science & Engineering Dept., La Jolla, CA
Stefanus Mantik , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 782-787
Stephen Knol , Northwestern University, Evanston, IL
Scott Hauck , Northwestern University, Evanston, IL
pp. 788-793
Session 48: Case Studies of New Design Methods
Peter Blinzer , Technical University of Braunschweig
Ulrich Holtmann , Synopsys, Inc., Mountain View, CA
pp. 794-799
In-Cheol Park , KAIST, Taejon, Korea
In-Hyung Kim , KAIST, Taejon, Korea
Jae-Yeol Kim , KAIST, Taejon, Korea
Jang-Ho Cho , KAIST, Taejon, Korea
Jong-Sun Kim , KAIST, Taejon, Korea
Jong-Yeol Lee , KAIST, Taejon, Korea
Jun-Sung Kim , KAIST, Taejon, Korea
Kun-Moo Lee , KAIST, Taejon, Korea
Kwang-11 Park , KAIST, Taejon, Korea
Kyu-Ho Park , KAIST, Taejon, Korea
Sang-Jun Nam , KAIST, Taejon, Korea
Seung-Hoon Hwang , KAIST, Taejon, Korea
Sung-won Seo , KAIST, Taejon, Korea
Yong-Hoon Lee , KAIST, Taejon, Korea
Young-Su Kwon , KAIST, Taejon, Korea
Byoung-Woon Kim , KAIST, Taejon, Korea
Chan-Soo Hwang , KAIST, Taejon, Korea
Chang-Ho Ryu , KAIST, Taejon, Korea
Chong-Min Kyung , KAIST, Taejon, Korea
Dae-Hyun Lee , KAIST, Taejon, Korea
Jin-Hyuk Yang , KAIST, Taejon, Korea
pp. 800-803
Luciano Lavagno , Politecnico di Torino - Cadence Eurpoeans Labs, Italy
Antonino Damiano , Magneti Marelli, Venaria Reale, Italy
Attila Jurecska , Magneti Marelli, Venaria Reale, Italy
Claudio Passeronge , Politecnico di Torino - Cadence Eurpoeans Labs, Italy
Claudio Sanso? , Politecnico di Torino, Italy
Tullio Cuatto , Politecnico di Torino, Italy
pp. 804-807
Sanjiv Narayan , Ambit Design Systems, Santa Clara
Jie Gong , Qualcomm Inc, San Diego, CA
Daniel D. Gajski , University of California, Irvine
pp. 812-817
Author Index (PDF)
pp. 818
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