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- DAC
- 1997
- Design Automation Conference, 34th Conference on (DAC'97)
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Design Automation Conference, 34th Conference on (DAC'97) Anaheim, CA June 09-June 13 ISBN: 0-89791-920-3 Table of Contents
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 | Session 1: Sequential Synthesis |
E. Pastor, Universitat Polit?cnica de Catalunya, Spain
M. A. Pe?, Universitat Polit?cnica de Catalunya, Spain pp. 16
 | Session 2: Interconnect Modeling |
I. M. Elfadel, IBM T. J. Watson Research Center, Yorktown Heights, NY
David D. Ling, IBM T. J. Watson Research Center, Yorktown Heights, NY pp. 28
 | Session 3: Novel Techniques for Software Scheduling |
 | Session 4: Embedded Tutorial |
 | Panel |
 | Session 5: Simulation Techniques for Microprocessors |
Ti-Yen Yen, Quickturn Design Systems, Inc., Mountain View, CA pp. 101
 | Session 6: Combinational Logic Synthesis |
Yibin Ye, Purdue University, West Lafayette, IN pp. 107
Stan Liao, Advanced Technology Group, Synopsys, Inc. pp. 117
 | Session 7: Interconnect Parasitic Extraction |
Zhijiang He, Carnegie Mellon University, Pittsburgh, PA pp. 137
Sharad Kapur, Bell Labs Lucent Technologies, Murray Hill, NJ pp. 141
 | Session 8: Advances in Timing Analysis for Embedded Software |
 | Session 9: Applications of Formal Verification |
Alok Jain, Carnegie Mellon University, Pittsburgh, PA pp. 161
Manish Pandey, Science, Carnegie Mellon University Pittsburgh, PA pp. 167
 | Session 10: System-Level Exploration and Refinement |
Ramesh Rao, University of Virginia, Charlottesville
Anup Ghosh, University of Virginia, Charlottesville pp. 184
Ole Bentz, Silicon Graphics, Inc., Mountain View, CA pp. 190
 | Session 11: Binary Decision Diagrams |
Youpyo Hong, University of Southern California, Los Angeles pp. 208
 | Session 12: Timing Analysis |
Tod Amon, Southwest Texas State University, San Marcos, TX
Taokuan Hu, Southwest Texas State University, San Marcos, TX
Jiwen Liu, Southwest Texas State University, San Marcos, TX pp. 226
 | Session 13: Embedded Tutorial |
 | Session 14: Panel |
 | Session 15: System-Level Optimization and Verification |
Ajay J. Daga, Interconnectix, a Mentor Graphics Business, Portland, OR pp. 240
Barry Shackleford, Hewlett-Packard Laboratories, Palo Alto, CA; Mitsubishi Electric Company, Yokohama, Japan pp. 246
 | Session 16: Formal Verification |
Florian Krohm, IBM Thomas J. Watson Research Center, Yorktown Heights, NY pp. 263
 | Session 17: Analog Simulation |
S. Mir, Instituto de Microelectr?nica de Sevilla, Sevilla, Spain
A. Rueda, Instituto de Microelectr?nica de Sevilla, Sevilla, Spain
T. Olbrich, AMS - Austria Mikro Systeme Int. AG, Austria
E. Peral?as, Instituto de Microelectr?nica de Sevilla, Sevilla, Spain
J. L. Huertas, Instituto de Microelectr?nica de Sevilla, Sevilla, Spain pp. 281
 | Session 18: Software Synthesis for Embedded Systems |
 | Session 19: Experiences in System Design and Education at Universities |
H. De Man, Katholieke Universiteit Leuven/IMEC, Belgium pp. 307
 | Session 20: Standard Cell and Physical Design Methods |
J. Khare, Level One Communications, Sacramento, CA
W. Maly, Carnegie Mellon University, Pittsburgh, PA
P. K. Nag, Carnegie Mellon University, Pittsburgh, PA
C. Ouyang, Carnegie Mellon University, Pittsburgh, PA pp. 321
 | Session 21: Modeling and Transformations in Synthesis |
Jian Li, University of Illinois, Urbana-Champaign pp. 341
Inki Hong, UCLA Computer Science Department, Los Angeles, CA pp. 347
 | Session 22: Statistical Power Estimation Techniques |
Qing Wu, University of Southern California, Los Angeles, CA pp. 371
 | Session 23: Co-Simulation |
 | Session 24: Panel |
 | Session 25: Emerging Technologies and Architecture for Low Power |
James Kao, Massachusetts Institute of Technology, Cambridge pp. 409
Chi-Ying Tsui, Hong Kong Univ. of Science and Technology, Clear Water Bay, H.K.
Kai-Keung Chan, Hong Kong Univ. of Science and Technology, Clear Water Bay, H.K.
Qing Wu, University of Southern California, Los Angeles, CA pp. 421
Qi Wang, University of Arizona. Tucson, AZ pp. 425
 | Session 26: High Level Synthesis for Low Power |
 | Session 27: Module Generation |
Avaneendra Gupta, University of Michigan, Ann Arbor; Intel Corporation, Santa Clara, CA pp. 452
Jaewon Kim, Quickturn Design Systems, Inc., Mountain View, CA
S. M. Kang, University of Illinois at Urbana-Champaign pp. 456
John Lakos, Mentor Graphics Corporation, Warren, NJ pp. 460
 | Session 28: BIST and DFT |
K. H. Tsai, University of California, Santa Barbara
J. Rajski, Mentor Graphics Corporation, Wilsonville, OR pp. 472
 | Session 29: Panel |
 | Session 30: DSP & Telecommunication System Design |
C. Hein, Lockheed Martin Advanced Technology Laboratories, Camden, NJ
J. Pridgen, Lockheed Martin Advanced Technology Laboratories, Camden, NJ
W. Kline, Lockheed Martin Advanced Technology Laboratories, Camden, NJ pp. 492
 | Session 31: Embedded Tutorial |
 | Session 32: Advances in Partitioning |
Ali Abbara, Institut National Polytechnique de Grenoble / CSI, France pp. 522
 | Session 33: Processor Test Techniques |
 | Session 34: Panel |
 | Session 35: Design Processes and Frameworks |
 | Session 36: Probabilistic Models of Input Data for Efficient Power Estimation |
 | Session 37: Hot Topics in Routing |
 | Session 38: Test Generation and Fault Simulation |
Oriol Roig, Universitat Polit?cnica de Catalunya, Spain pp. 620
 | Session 39: Panel |
 | Session 40: Deep Submicron Modeling and Analysis |
David Noice, Cadence Design Systems, Inc., San Jose, CA pp. 627
Howard H. Chen, Thomas J. Watson Research Center, Yorktown Heights, NY
David D. Ling, Thomas J. Watson Research Center, Yorktown Heights, NY pp. 638
 | Session 41: Technology-Dependent Optimization for Performance and Power |
Chang Wu, University of California, Los Angeles pp. 644
C. L. Liu, Univ. of Illinois at Urbana-Champaign pp. 656
Takashi Ishioka, Semiconductor DA & TEST Engineering Center, Kawasaki, Japan
Masami Murakata, Semiconductor DA & TEST Engineering Center, Kawasaki, Japan pp. 666
 | Session 42: CAD Issues for Micro-Electro-Mechanical Systems |
A. Poppe, Technical University of Budapest, Hungary
V. Szekely, Technical University of Budapest, Hungary
M. Renez, Technical University of Budapest, Hungary
K. Hofmann, Darmstadt University of Technology, Germany
M. Glesner, Darmstadt University of Technology, Germany pp. 674
N. Aluru, Massachusetts Institute of Technology, Cambridge, MA
J. White, Massachusetts Institute of Technology, Cambridge, MA pp. 686
 | Session 43: Hardware/Software Partitioning |
Rolf Ernst, Technische Universit?t Braunschweig, Germany pp. 691
 | Session 44: Embedded Tutorial |
 | Session 45: Designing High Performance and Low Power Microprocessors Using Full Custom Techniques |
 | Session 46: Formal Verification Techniques |
 | Session 47: Placement Techniques |
T. Chan, UCLA Mathematics Dept., Los Angeles, CA
I. Markov, UCLA Mathematics Dept., Los Angeles, CA
K. Yan, UCLA Computer Science Dept., Los Angeles, CA pp. 752
Jin Xu, University of California, San Diego pp. 762
 | Session 48: Panel |
 | Session 49: Heterogeneous System Analysis |
C. Fan, University of California, San Diego pp. 768
Clifford Liem, Central Ramp;D, SGS-Thomson Microelectronics, France; Laboratoire TIMA, L'Insitut National Polytechnique de Grenoble, France
Marco Cornero, Central Ramp;D, SGS-Thomson Microelectronics, France
Pierre Paulin, Central Ramp;D, SGS-Thomson Microelectronics, France
Ahmed Jerraya, Laboratoire TIMA, L'Insitut National Polytechnique de Grenoble, France
Jean Lopez, Thomson Consumer Electronic Components, France pp. 780 Usage of this product signifies your acceptance of the Terms of Use.
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