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27th ACM/IEEE Design Automation Conference (DAC '90)
Orlando, FL, USA
June 24-June 28
ISBN: 0-89791-363-9
| ASCII Text | x | ||
| "27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4)," Design Automation Conference, pp. 0_1-, 27th ACM/IEEE Design Automation Conference (DAC '90), 1990. | |||
| BibTex | x | ||
| @article{ 10.1109/DAC.1990.114953, author = {}, title = {27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4)}, journal ={Design Automation Conference}, volume = {0}, year = {1990}, isbn = {0-89791-363-9}, pages = {0_1-}, doi = {http://doi.ieeecomputersociety.org/10.1109/DAC.1990.114953}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Design Automation Conference TI - 27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4) SN - 0-89791-363-9 SP0_1 EP PY - 1990 KW - VHDL KW - HDL validation KW - placement KW - binary decision diagrams KW - scheduling KW - mapping KW - allocation KW - timing-driven layout KW - data management KW - version control KW - data path optimization algorithms KW - floorplanning KW - formal methods KW - design verification KW - logic synthesis KW - testability KW - layout synthesis KW - MOS digital cells KW - software engineering KW - design automation KW - Boolean methods KW - timing KW - routing optimization KW - layout compactors KW - circuit simulation KW - logic simulation acceleration KW - data path synthesis KW - behavioral synthesis KW - performance-constrained routing KW - functional models KW - decomposition KW - partitioning KW - combinational test generation KW - channel-oriented multilayer routing VL - 0 JA - Design Automation Conference ER - | |||
Index Terms:
VHDL, HDL validation, placement, binary decision diagrams, scheduling, mapping, allocation, timing-driven layout, data management, version control, data path optimization algorithms, floorplanning, formal methods, design verification, logic synthesis, testability, layout synthesis, MOS digital cells, software engineering, design automation, Boolean methods, timing, routing optimization, layout compactors, circuit simulation, logic simulation acceleration, data path synthesis, behavioral synthesis, performance-constrained routing, functional models, decomposition, partitioning, combinational test generation, channel-oriented multilayer routing
Citation:
"27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4)," dac, pp.0_1-, 27th ACM/IEEE Design Automation Conference (DAC '90), 1990
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