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2010 Third International Joint Conference on Computational Science and Optimization
VectorSTM: Software Transactional Memory without Atomic Instructions
Huangshan, Auhui, China
May 28-May 31
ISBN: 978-0-7695-4030-6
| ASCII Text | x | ||
| Lin Peng, Lun-guo Xie, Xiao-qiang Zhang, Xin-yan Xie, "VectorSTM: Software Transactional Memory without Atomic Instructions," 2012 Fifth International Joint Conference on Computational Sciences and Optimization, vol. 2, pp. 278-282, 2010 Third International Joint Conference on Computational Science and Optimization, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/CSO.2010.145, author = {Lin Peng and Lun-guo Xie and Xiao-qiang Zhang and Xin-yan Xie}, title = {VectorSTM: Software Transactional Memory without Atomic Instructions}, journal ={2012 Fifth International Joint Conference on Computational Sciences and Optimization}, volume = {2}, year = {2010}, isbn = {978-0-7695-4030-6}, pages = {278-282}, doi = {http://doi.ieeecomputersociety.org/10.1109/CSO.2010.145}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 Fifth International Joint Conference on Computational Sciences and Optimization TI - VectorSTM: Software Transactional Memory without Atomic Instructions SN - 978-0-7695-4030-6 SP278 EP282 A1 - Lin Peng, A1 - Lun-guo Xie, A1 - Xiao-qiang Zhang, A1 - Xin-yan Xie, PY - 2010 KW - multi-core processors KW - software transactional memory KW - vector timestamp KW - atomic instructions VL - 2 JA - 2012 Fifth International Joint Conference on Computational Sciences and Optimization ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSO.2010.145
Transactional Memory(TM) is a promising way to coordinate concurrent threads in multi-core processors. Software transactional memory (STM) can run on conventional processors without additional hardware support. In this paper we propose VectorSTM which reduces the cost of centralized concurrency control. VectorSTM employs distributed vector timestamps instead of a single global timestamp to track the progress of transactions. Conflict detecting and transaction committing are done by polling thread local bloom filter queues which are indexed by the vector timestamps. Without employing any atomic instructions, VectorSTM reduces synchronization cost on the global timestamp variable and provides more concurrency. VectorSTM provides privatization safety which is critical to software transactional memory safety and avoids live lock and starvation by effective contention manager. We evaluate VectorSTM with STAMP benchmarks and the results show that the design offer superior performance or stronger semantics than TL2 and RingSTM algorithm. On particular tests VectorSTM outperforms TL2 and RingSTM 27% and 41% respectively with 8 threads running.
Index Terms:
multi-core processors, software transactional memory, vector timestamp, atomic instructions
Citation:
Lin Peng, Lun-guo Xie, Xiao-qiang Zhang, Xin-yan Xie, "VectorSTM: Software Transactional Memory without Atomic Instructions," cso, vol. 2, pp.278-282, 2010 Third International Joint Conference on Computational Science and Optimization, 2010
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