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2009 WRI World Congress on Computer Science and Information Engineering
Multiple-Valued Memory Design by Standard BiCMOS Technique
Los Angeles, California USA
March 31-April 02
ISBN: 978-0-7695-3507-4
A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction-bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.
Index Terms:
NDR, HBT, BiCMOS, MOS-HBT-NDR
Citation:
Dong-Shong Liang, Kwang-Jow Gan, Jenq-Jong Lu, Cheng-Chi Tai, Cher-Shiung Tsai, Geng-Huang Lan, Yaw-Hwang Chen, "Multiple-Valued Memory Design by Standard BiCMOS Technique," csie, vol. 3, pp.596-599, 2009 WRI World Congress on Computer Science and Information Engineering, 2009
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