Los Angeles, CA
March 31, 2009 to April 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.520
In this paper, we present the design of a GALS wrapper used in Network on Chip (NoC) based on standard cells. The GALS wrapper includes two communication ports, 4-phase handshake circuits, data buffer and signal synchronizer. The detailed design methodology of GALS wrapper is given and the circuits are validated with Verilog-HDL and implemented in FPGA. The simulation results show that the wrapper provides fast and reliable asynchronous communication services for the subsystems working with different clocks in NoC.
GALS, Handshake circuit, Synchronizer, Network on Chip
Wu Ning, Ge Fen, Wu Fei, "Design of a GALS Wrapper for Network on Chip", CSIE, 2009, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, pp. 592-595, doi:10.1109/CSIE.2009.520