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2009 WRI World Congress on Computer Science and Information Engineering
Low Power Design of a Grating Detection System Chip
Los Angeles, California USA
March 31-April 02
ISBN: 978-0-7695-3507-4
This paper forwards a low power design of a grating detection system chip (GDC) on length and angle precision measurement. Traditional grating detection methods are complex, costly, and suffer big power consumption for the complex divide circuit scheme and CPU software compensation. GDC achieves the whole grating detection system function, high speed orthogonal signal handling in a single chip with very low power consumption. It is an application-specific integrated circuit (ASIC), integrated micro controller unit (MCU), power management unit (PMU), two LCD controller, keyboard interface, grating detection unit and other peripherals. Working at 10MHz, GDC can afford 5MHz internal sampling rate and 1.25MHz orthogonal signal from grating sensor. By implementing low power system design, orthogonal signal dividing and Low power divider design, GDC consumes 0.9mw in test mode and 0.2mw in real mode. GDC is tape out in HJTC 180nm process with evaluation kit and demo system developed.
Citation:
Li-gang Hou, Xiao-hong Peng, Wu-chen Wu, "Low Power Design of a Grating Detection System Chip," csie, vol. 3, pp.550-554, 2009 WRI World Congress on Computer Science and Information Engineering, 2009
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