Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.967
A statistical dynamic timing analysis framework is presented to study the impact of catastrophic defects and process variation on the delay behavior of a digital circuit considering the effect of gate switching on delays. It uses object-oriented programming and levelized code generation techniques to achieve fast runtimes with linear time complexity as the number of gates increases. The generated functional delay model along with experiments and statistical modules are compiled to machine code before execution; and random transition vectors approximate the delay profiles useful for virtual speed grading and yield estimation.
Statistical Timing Analysis, Dynamic Timing Analysis, Process Variations, Compiled Code Simulation
Seyed-Abdollah Aftabjahani, Linda Milor, "Fast Variation-Aware Statistical Dynamic Timing Analysis", CSIE, 2009, Computer Science and Information Engineering, World Congress on, Computer Science and Information Engineering, World Congress on 2009, pp. 488-492, doi:10.1109/CSIE.2009.967