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2009 WRI World Congress on Computer Science and Information Engineering
A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process
Los Angeles, California USA
March 31-April 02
ISBN: 978-0-7695-3507-4
In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectre with 0.13μm CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz Bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit achieves a NF of 2.9 dB at the center frequency and consumes only 3.38 mW of power when driven from 1.2 Vpower supply. To the best of the authors’ knowledge, a single stage LNA operating at such high frequency is yet to be reported.
Index Terms:
36.1 GHz, Single Stage, Low Noise Amplifier, LNA, Passive Output Matching, 0.13µm CMOS Process
Citation:
S.M. Shahriar Rashid, Sheikh Nijam Ali, Apratim Roy, A.B.M.H. Rashid, "A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process," csie, vol. 3, pp.480-483, 2009 WRI World Congress on Computer Science and Information Engineering, 2009
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