The Community for Technology Leaders
RSS Icon
Subscribe
Los Angeles, CA
March 31, 2009 to April 2, 2009
ISBN: 978-0-7695-3507-4
pp: 480-483
ABSTRACT
In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectre with 0.13μm CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz Bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit achieves a NF of 2.9 dB at the center frequency and consumes only 3.38 mW of power when driven from 1.2 Vpower supply. To the best of the authors’ knowledge, a single stage LNA operating at such high frequency is yet to be reported.
INDEX TERMS
36.1 GHz, Single Stage, Low Noise Amplifier, LNA, Passive Output Matching, 0.13µm CMOS Process
CITATION
S.M. Shahriar Rashid, Sheikh Nijam Ali, Apratim Roy, A.B.M.H. Rashid, "A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process", CSIE, 2009, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, pp. 480-483, doi:10.1109/CSIE.2009.86
18 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool