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Los Angeles, CA
March 31, 2009 to April 2, 2009
ISBN: 978-0-7695-3507-4
pp: 465-469
ABSTRACT
Traditional CPU instructions provide limited support to the byte permutation operation which is frequently used in the various symmetric encryption algorithms. Due to this reason, researcher Ruby B. Lee at Princeton University presented the byte permutation instructions and proved that the byte permutation instructions played an important role on improving the performance of cryptographic algorithms for general processors. Our attention is emphasized at the hardware implementation of the byte permutation instruction, and we present a byte permutation functional unit which is validated on FPGA of ALTERA’s Cyclone EP1C12Q240C6N. In the end, we present the throughput of the AES algorithm on the hardware implementation. And it is proved that the throughput is nine times higher than the available hardware implementation of AES on a universal architecture.
INDEX TERMS
Cryptographic algorithm, bit permutation operation, functional unit, FPGA validation
CITATION
Jing Liang, Qin Wang, "The Hardware Implementation of Byte Permutation Instruction of an Embedded Processor", CSIE, 2009, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, pp. 465-469, doi:10.1109/CSIE.2009.166
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