The Community for Technology Leaders
RSS Icon
Subscribe
Los Angeles, CA
March 31, 2009 to April 2, 2009
ISBN: 978-0-7695-3507-4
pp: 458-464
ABSTRACT
In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.
INDEX TERMS
Parallel processing, multi-DSP, real-time processing, hardware architecture
CITATION
Jun Wang, Wei Li, Wei Wu, "Design Methods of Multi-DSP Parallel Processing System", CSIE, 2009, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, pp. 458-464, doi:10.1109/CSIE.2009.40
5 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool