Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.894
An adiabatic 32X32 content-addressable memory (CAM) are designed in this paper, which consists of a CAM storage-cell array, address decoders, bit-lines drivers, and match-line driving circuits. All circuits except for CAM storage cells and driving control circuits for match lines are realized using CPAL (Complementary Pass-Transistor Adiabatic Logic) circuits. The charge of large node capacitances on match lines, bit lines, word lines, and address lines is well recovered in fully adiabatic manner. For comparison, a conventional 32X32 CAM is also implemented using the similar structure. The two CAM cores have been integrated in a test chip with Chartered 0.35um CMOS process. Based on the post-layout simulations, the adiabatic CAM can work very well, and it attains about 86% energy saves compared to the conventional CMOS implementation at 100MHz.
Content-addressable memories, Adiabatic circuits, Low power
Qingbo Xu, Lifang Ye, Jianping Hu, Lijun Huang, "The Implementation of Low-Power CAM with Fully Adiabatic Driving for Large Node Capacitances", CSIE, 2009, Computer Science and Information Engineering, World Congress on, Computer Science and Information Engineering, World Congress on 2009, pp. 413-417, doi:10.1109/CSIE.2009.894