Los Angeles, CA
March 31, 2009 to April 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.826
This paper presents an adiabatic tree multiplier based on modified Booth algorithm, which operates in a single-phase power-clock. All circuits are realized using improved CAL (Clocked Adiabatic Logic) circuits with TSMC 0.18um CMOS process. The proposed single-phase adiabatic Booth encoder attains energy savings of 82% at 50MHz and 70% at 300MHz, compared with its CMOS counterpart. The single-phase adiabatic partial product generator and 4-2 compressors based on the gate level attain energy savings of 80% and 76% as compared to the conventional CMOS implementations at 200MHz, respectively.
Multipliers, Modified Booth algorithm, Single-phase adiabatic circuits
Weiqiang Zhang, Li Su, Xiaoyan Luo, Jinghong Fu, Jianping Hu, "Single-Phase Adiabatic Tree Multipliers with Modified Booth Algorithm", CSIE, 2009, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, pp. 402-407, doi:10.1109/CSIE.2009.826