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2009 WRI World Congress on Computer Science and Information Engineering
Single-Phase Adiabatic Tree Multipliers with Modified Booth Algorithm
Los Angeles, California USA
March 31-April 02
ISBN: 978-0-7695-3507-4
This paper presents an adiabatic tree multiplier based on modified Booth algorithm, which operates in a single-phase power-clock. All circuits are realized using improved CAL (Clocked Adiabatic Logic) circuits with TSMC 0.18um CMOS process. The proposed single-phase adiabatic Booth encoder attains energy savings of 82% at 50MHz and 70% at 300MHz, compared with its CMOS counterpart. The single-phase adiabatic partial product generator and 4-2 compressors based on the gate level attain energy savings of 80% and 76% as compared to the conventional CMOS implementations at 200MHz, respectively.
Index Terms:
Multipliers, Modified Booth algorithm, Single-phase adiabatic circuits
Citation:
Weiqiang Zhang, Li Su, Xiaoyan Luo, Jinghong Fu, Jianping Hu, "Single-Phase Adiabatic Tree Multipliers with Modified Booth Algorithm," csie, vol. 3, pp.402-407, 2009 WRI World Congress on Computer Science and Information Engineering, 2009
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