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Los Angeles, CA
March 31, 2009 to April 2, 2009
ISBN: 978-0-7695-3507-4
pp: 387-391
ABSTRACT
This paper describes the principle with the quadrature reference clocks in dual-loop clock and data recovery circuit. The traditional scheme of generating quadrature clock is analyzed, and a new algorithm with phase interpolation and selection is presented after the modification of the circuit in existence. This algorithm enhances the jitter tolerance of input datum. The scheme is realized with CMOS circuit, as well as the entire circuit is simulated with Cadence Spectre in 0.18um CMOS technology.
CITATION
Deng Junyong, Zeng Zecang, "Design of Multi-phase Clock Generation and Selection Circuit for CDR", CSIE, 2009, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, pp. 387-391, doi:10.1109/CSIE.2009.459