Los Angeles, California USA
Mar. 31, 2009 to Apr. 2, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSIE.2009.459
This paper describes the principle with the quadrature reference clocks in dual-loop clock and data recovery circuit. The traditional scheme of generating quadrature clock is analyzed, and a new algorithm with phase interpolation and selection is presented after the modification of the circuit in existence. This algorithm enhances the jitter tolerance of input datum. The scheme is realized with CMOS circuit, as well as the entire circuit is simulated with Cadence Spectre in 0.18um CMOS technology.
Deng Junyong, Jiang Lin, Zeng Zecang, "Design of Multi-phase Clock Generation and Selection Circuit for CDR", CSIE, 2009, Computer Science and Information Engineering, World Congress on, Computer Science and Information Engineering, World Congress on 2009, pp. 387-391, doi:10.1109/CSIE.2009.459