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2009 WRI World Congress on Computer Science and Information Engineering
Design of Multi-phase Clock Generation and Selection Circuit for CDR
Los Angeles, California USA
March 31-April 02
ISBN: 978-0-7695-3507-4
This paper describes the principle with the quadrature reference clocks in dual-loop clock and data recovery circuit. The traditional scheme of generating quadrature clock is analyzed, and a new algorithm with phase interpolation and selection is presented after the modification of the circuit in existence. This algorithm enhances the jitter tolerance of input datum. The scheme is realized with CMOS circuit, as well as the entire circuit is simulated with Cadence Spectre in 0.18um CMOS technology.
Citation:
Deng Junyong, Jiang Lin, Zeng Zecang, "Design of Multi-phase Clock Generation and Selection Circuit for CDR," csie, vol. 3, pp.387-391, 2009 WRI World Congress on Computer Science and Information Engineering, 2009
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