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Los Angeles, CA
March 31, 2009 to April 2, 2009
ISBN: 978-0-7695-3507-4
pp: 442-446
ABSTRACT
Nios II is the soft-core 32 bits RISC processor of the Altera Corporation which can be implied in its FPGA. Users can design their own peripherals accord with Avalon Bus specification in Nios II system. A new design method for Plus Width Module (PWM) peripheral is presented, which is completed by Verilog HDL. Comparing to the common PWM module, this new PWM module use the hardware units(logic elements in FPGAs) to calculate the counts of the frequency and the duty cycle, the software only write the period (Hz units) to the period register and the duty cycle (% units) to its register. This presented peripheral for the Nios II system is used successfully in FPGA, and the CPU's runtime can be saved effectively.
INDEX TERMS
PWM, Avalon Bus, Nios II, Verilog HDL
CITATION
Yang Xu, Min Xiang, "Design a New Type PWM Peripherals in Nios II", CSIE, 2009, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, pp. 442-446, doi:10.1109/CSIE.2009.535
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