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Proceedings of the 4th international conference on Hardware/software codesign and system synthesis (CODES+ISSS '06)
Seoul, Korea
October 22-October 25
ISBN: 1-59593-370-0
Table of Contents
Session A1: HW/SW Design Exploration for Multimedia Applications
Yves Vanderperren, Katholieke Universiteit Leuven, Heverlee, Belgium
Wolfgang Mueller, Paderborn University, Paderborn, Germany
pp. 1-1
Seiji Kawamura, AutoNetworks Technologies, Ltd., Yokkaichi, Japan
Yoshimi Furukawa, Shibaura Institute of Technology, Saitama, Japan
pp. 2-2
Marco Bekooij, Philips Research, Eindhoven, The Netherlands
Gerard Smit, University of Twente, Enschede, The Netherlands
Pierre Jansen, University of Twente, Enschede, The Netherlands
Maarten Wiggers, University of Twente, Enschede, The Netherlands
pp. 10-15
Sudarshan Banerjee, University of California, Irvine, CA
Nikil Dutt, University of California, Irvine, CA
Nalini Venkatasubramanian, University of California, Irvine, CA
Minyoung Kim, University of California, Irvine, CA
pp. 16-21
Session A2: Low Power Scheduling and Estimation Techniques
Karsten Albers, University of Oldenburg, Oldenburg, Germany
Frank Slomka, University of Oldenburg, Oldenburg, Germany
Henrik Lipskoch, University of Oldenburg, Oldenburg, Germany
pp. 22-27
Chandra Krintz, UC Santa Barbara, Santa Barbara, CA
Selim Gurun, UC Santa Barbara, Santa Barbara, CA
pp. 28-33
Diana Marculescu, Carnegie Mellon University, Pittsburgh, PA
Puru Choudhary, Carnegie Mellon University, Pittsburgh, PA
pp. 34-39
Session A3: System-Level Performance Issues
Razvan Racu, Technical University of Braunschweig, Germany
Rolf Ernst, Technical University of Braunschweig, Germany
Arne Hamann, Technical University of Braunschweig, Germany
pp. 40-45
Robert P. Dick, Northwestern University, Evanston, Illinois
Ai-Hsin Liu, Northwestern University, Evanston, Illinois
pp. 46-51
Session A4: Transaction-Level Modeling and Exploration
D. Quaglia, Universit? di Verona, Verona, Italy
F. Fummi, Universit? di Verona, Verona, Italy
N. Bombieri, Universit? di Verona, Verona, Italy
pp. 58-63
Junyu Peng, University of California, Irvine, CA, USA
Andreas Gerstlauer, University of California, Irvine, CA, USA
Daniel D. Gajski, University of California, Irvine, CA, USA
Rainer D?mer, University of California, Irvine, CA, USA
Dongwan Shin, University of California, Irvine, CA, USA
pp. 64-69
Rainer D?mer, University of California, Irvine, USA
Gunar Schirner, University of California, Irvine, USA
pp. 70-75
Session A5: Architecture and Modeling for Network-on-Chip
Gereon Weiss, University of Karlsruhe, Karlsruhe, Germany
Joerg Henkel, University of Karlsruhe, Karlsruhe, Germany
Mohammad Abdullah Al Faruque, University of Karlsruhe, Karlsruhe, Germany
pp. 76-81
Nader Bagherzadeh, University of California, Irvine, Irvine, CA, USA
Seung Eun Lee, University of California, Irvine, Irvine, CA, USA
pp. 82-87
Tanguy Risset, CITI - INSA Lyon, Villeurbanne Cedex, France
Antoine Fraboulet, CITI - INSA Lyon, Villeurbanne Cedex, France
Antoine Scherrer, LIP - ENS Lyon, Lyon cedex 7, France
pp. 88-93
Session A6: Embedded Security and Reliability
B. A. White, University of Waterloo, Waterloo, Ont Canada
C. H. Gebotys, University of Waterloo, Waterloo, Ont Canada
pp. 94-99
Sri Parameswaran, University of New South Wales and National ICT Australia, Sydney NSW, Australia
Roshan G. Ragel, University of New South Wales and National ICT Australia, Sydney NSW, Australia
pp. 100-105
Niraj K. Jha, Princeton University, Princeton, NJ
Srivaths Ravi, NEC Laboratories America, Princeton, NJ
Anand Raghunathan, NEC Laboratories America, Princeton, NJ
Divya Arora, Princeton University, Princeton, NJ
pp. 106-111
Session A7: Advanced Techniques for High-Level Synthesis and Physical Design
Kamal Khouri, Freescale Semiconductor Inc., Austin, TX, USA
Fadi Kurdahi, University of California, Irvine, Irvine, CA, USA
Magdy Abadir, Freescale Semiconductor Inc., Austin, TX, USA
Nikil Dutt, University of California, Irvine, Irvine, CA, USA
Aseem Gupta, University of California, Irvine, Irvine, CA, USA
pp. 118-123
Taewhan Kim, Seoul National University, Seoul, Korea
Pilok Lim, Seoul National University, Seoul, Korea
pp. 124-129
Session A8: Design Optimization for Network-on-Chip
Andrei Ruadulescu, Philips Research, Eindhoven, The Netherlands
Kees Goossens, Philips Research, Eindhoven, The Netherlands
Giovanni De Micheli, LSI, EPFL, Switzerland
Srinivasan Murali, Stanford University, Stanford, CA, USA
Martijn Coenen, Philips Research, Eindhoven, The Netherlands
pp. 130-135
Karam S. Chatha, Arizona State University, Tempe, AZ
Krishnan Srinivasan, Arizona State University, Tempe, AZ
pp. 136-141
Vincenzo Catania, DIIT, University of Catania, Catania, Italy
Rickard Holsmark, J?nk?ping University, Sweden
Shashi Kumar, J?nk?ping University, Sweden
Maurizio Palesi, University of Catania, Italy
pp. 142-147
Session A9: Application-Specific Code Optimization
Christoph Schumacher, RWTH Aachen University, Germany
Gerd Ascheid, RWTH Aachen University, Germany
Heinrich Meyr, RWTH Aachen University, Germany
Rainer Leupers, RWTH Aachen University, Germany
Hans van Someren, Associated Compiler Experts bv, Amsterdam, The Netherlands
Manuel Hohenauer, RWTH Aachen University, Germany
pp. 148-153
Nobu Matsumoto, Semiconductor Company, Toshiba Corporation, Saiwai-Ku, Kawasaki, Japan
Yutaka Ota, Semiconductor Company, Toshiba Corporation, Saiwai-Ku, Kawasaki, Japan
Masaharu Imai, Osaka University, Suita, Osaka, Japan
Keishi Sakanushi, Osaka University, Suita, Osaka, Japan
Yoshinori Takeuchi, Osaka University, Suita, Osaka, Japan
Masaki Nakagawa, Semiconductor Company, Toshiba Corporation, Saiwai-Ku, Kawasaki, Japan
Tanaka Hiroaki, Osaka University, Suita, Osaka, Japan
pp. 154-159
Koen Bertels, Delft University of Technology, Delft, The Netherlands
Elena Moscu Panainte, Delft University of Technology, Delft, The Netherlands
Yana Yankova, Delft University of Technology, Delft, The Netherlands
Stamatis Vassiliadis, Delft University of Technology, Delft, The Netherlands
Carlo Galuzzi, Delft University of Technology, Delft, The Netherlands
pp. 160-165
Special session A10: Programming Models for Multiprocessor Systems: From Supercomputing Programming to Multiprocessors on a Chip
Rainer Leupers, Aachen Univ. of Technology, Germany
Lothar Thiele, Swiss Federal Institute of Technology, (ETH) Z?rich, Switzerland
Ahmed A. Jerraya, TIMA INPG, Grenoble, France
Piero Vicini, INFN Dip. Fisica Univ. Roma "La Sapienza", Roma, Italy
Pier S. Paolucci, INFN Dip. Fisica Univ. Roma, ATMEL Roma, Italy
pp. 167-172
Hideki Saito, Intel Corporation, Santa Clara, CA, USA
Alexander V. Veidenbaum, University of California at Irvine, Irvine, CA, USA
Xinmin Tian, Intel Corporation, Santa Clara, CA, USA
Milind Girkarmark, Intel Corporation, Santa Clara, CA, USA
Alexandru Nicolau, University of California at Irvine, Irvine, CA, USA
Arun Kejariwal, University of California at Irvine, Irvine, CA, USA
pp. 173-180
Christopher D. Gill, Washington University, St. Louis, MO, USA
pp. 181-186
Session A11: Simulation, Optimization, and Acceleration
Rajesh Gupta, University of California San Diego
Dohyung Kim, University of California San Diego
Jeffrey Namkung, University of California San Diego
pp. 187-192
Xinping Zhu, Northeastern University, Boston, MA, USA
Joseph D'Errico, Cavium Networks, Inc., Marlborough, MA, USA
Wei Qin, Boston University, Boston, MA, USA
pp. 193-198
Massoud Pedram, University of Southern California, Los Angeles, CA
Kimish Patel, University of Southern California, Los Angeles, CA
Wonbok Lee, University of Southern California, Los Angeles, CA
pp. 199-204
Session A12: System-Level Design of MPSoC
Cristina Silvano, Politecnico di Milano, Milano, Italy
Donatella Sciuto, Politecnico di Milano, Milano, Italy
Dario Bruschi, Politecnico di Milano, Milano, Italy
Giovanni Beltrame, Politecnico di Milano, Milano, Italy
pp. 205-210
Todor Stefanov, Leiden University, The Netherlands
Ed Deprettere, Leiden University, The Netherlands
Hristo Nikolov, Leiden University, The Netherlands
pp. 211-216
Andrea Erdos, The University of New South Wales, Sydney, NSW, Australia
Sri Parameswaran, The University of New South Wales, Sydney, NSW, Australia
Seng Lin Shee, The University of New South Wales, Sydney, NSW, Australia
pp. 217-222
Session A13: System-Level Optimization
Vincenzo Catania, DIIT, Universit? di Catania, Catania, Italy
Giuseppe Ascia, DIIT, Universit? di Catania, Catania, Italy
Maurizio Palesi, DIIT, Universit? di Catania, Catania, Italy
Davide Patti, DIIT, Universit? di Catania, Catania, Italy
Alessandro G. Di Nuovo, DIIT, Universit? di Catania, Catania, Italy
pp. 223-228
Yongseok Choi, Seoul National University, Korea
EuiYoung Chung, Yonsei University, Korea
Naehyuck Chang, Seoul National University, Korea
Sung Woo Chung, Korea University, Korea
Chanik Park, Samsung Electronics, Korea
Yongsoo Joo, Seoul National University, Korea
pp. 229-234
Jeong-Taek Kong, Samsung Electronics CO., LTD
Bum-Seok Yoo, Samsung Electronics CO., LTD
Donghyun Song, Samsung Electronics CO., LTD
Hye Jeong Nam, Samsung Electronics CO., LTD
Jaehyung Hwang, Samsung Electronics CO., LTD
Janghwan Kim, Samsung Electronics CO., LTD
Sangwoo Lee, Samsung Electronics CO., LTD
SooKwan Eo, Samsung Electronics CO., LTD
Sungjoo Yoo, Samsung Electronics CO., LTD
Kyu-Myung Choi, Samsung Electronics CO., LTD
HoonSang Jin, Samsung Electronics CO., LTD
Jeongeun Kim, Samsung Electronics CO., LTD
Sheayun Lee, Samsung Electronics CO., LTD
Sungpack Hong, Samsung Electronics CO., LTD
pp. 235-240
Session A14: Architecture Exploration
Hui Guo, University of New South Wales, Sydney, NSW, Australia
Sri Parameswaran, University of New South Wales, Sydney, NSW, Australia
Aleksandar Ignjatovic, University of New South Wales, Sydney, NSW, Australia
Swarnalatha Radhakrishnan, University of New South Wales, Sydney, NSW, Australia
pp. 241-246
TingTing Hwang, National Tsing Hua University HsinChu, Taiwan, R.O.C
Po-Yuan Chen, National Tsing Hua University HsinChu, Taiwan, R.O.C
Wen-Wen Hsieh, National Tsing Hua University HsinChu, Taiwan, R.O.C
pp. 247-252
T. Grabner, IMEC vzw, Leuven, Belgium
F. Catthoor, IMEC vzw, Leuven, Belgium
M. Miranda, IMEC vzw, Leuven, Belgium
P. Roussel, IMEC vzw, Leuven, Belgium
A. Papanikolaou, IMEC vzw, Leuven, Belgium
pp. 253-258
Robert Brodersen, University of California, Berkeley
Artem Tkachenko, University of California, Berkeley
Hayden Kwok-Hay So, University of California, Berkeley
pp. 259-264
Special Session A15: Industry Solutions to Emerging Embedded Systems
Session A16: Synthesis Techniques for Accelerators
Scott Mahlke, University of Michigan, Ann Arbor, MI
Kevin Fan, University of Michigan, Ann Arbor, MI
Manjunath Kudlur, University of Michigan, Ann Arbor, MI
pp. 270-275
Scott Mahlke, University of Michigan, Ann Arbor, MI
Manjunath Kudlur, University of Michigan, Ann Arbor, MI
Hyunchul Park, University of Michigan, Ann Arbor, MI
Kevin Fan, University of Michigan, Ann Arbor, MI
pp. 276-281
Pramod Chandraiah, University of California, Irvine
Mehrdad Reshadi, University of California, Irvine
Daniel Gajski, University of California, Irvine
Bita Gorjiara, University of California, Irvine
pp. 282-287
Session A17: Communication Synthesis and Analysis for MPSoC
Matthias Ivers, Technical University of Braunschweig, Germany
Rolf Ernst, Technical University of Braunschweig, Germany
Simon Schliecker, Technical University of Braunschweig, Germany
pp. 288-293
Young-Hwan Park, University of California, Irvine, CA
Fadi J. Kurdahi, University of California, Irvine, CA
Nikil Dutt, University of California, Irvine, CA
Sudeep Pasricha, University of California, Irvine, CA
pp. 300-305
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