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International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'04)
Stockholm, Sweden
September 08-September 10
ISBN: 1-58113-937-3
Table of Contents
Introduction
Keynote
Session A1: Special Session on Organic Computing
Session B1: New Design Techniques for Application Specific Processors
Swarnalatha Radhakrishnan, University of New South Wales
Hui Guo, University of New South Wales
Sri Parameswaran, University of New South Wales
pp. 12-17
Scott J. Weber, University of California at Berkeley
Matthew W. Moskewicz, University of California at Berkeley
Matthias Gries, University of California at Berkeley
Christian Sauer, Infineon Technologies
Kurt Keutzer, University of California at Berkeley
pp. 18-23
Session A2: Advances in Software and Hardware Synthesis Techniques for DSP Applications
F. Rivera, Universidad Complutense
M. Sanchez-Elez, Universidad Complutense
M. Fernandez, Universidad Complutense
R. Hermida, Universidad Complutense
N. Bagherzadeh, University of California at Irvine
pp. 30-35
Vladimir Kotlyar, Sandbridge Technologies, Inc.
Mayan Moudgill, Sandbridge Technologies, Inc.
pp. 36-41
Gwenolé Corre, University of South Brittany
Eric Senn, University of South Brittany
Pierre Bomel, University of South Brittany
Nathalie Julien, University of South Brittany
Eric Martin, University of South Brittany
pp. 42-47
Session B2: Multiprocessor SoC: Design Strategies and Programming Models
Pierre G. Paulin, STMicroelectronics
Chuck Pilkington, STMicroelectronics
Michel Langevin, STMicroelectronics
Essaid Bensoudane, STMicroelectronics
Gabriela Nicolescu, Ecole Polytechnique de Montreal
pp. 48-53
JoAnn M. Paul, Carnegie Mellon University
Donald E. Thomas, Carnegie Mellon University
Alex Bobrek, Carnegie Mellon University
pp. 54-59
Basant Kumar Dwivedi, Indian Institute of Technology Delhi
Anshul Kumar, Indian Institute of Technology Delhi
M. Balakrishnan, Indian Institute of Technology Delhi
pp. 60-65
Panel 1
Session A3: New Modeling Approaches and Their Application
Manish Vachharajani, Princeton University
Neil Vachharajani, Princeton University
Sharad Malik, Princeton University
David I. August, Princeton University
pp. 86-91
Qiang Zhu, Fujitsu Laboratories LTD.
Ryosuke Oishi, Fujitsu Laboratories LTD.
Takashi Hasegawa, Fujitsu Limited
Tsuneo Nakata, Fujitsu Laboratories LTD.
pp. 92-97
Session B3: Energy-Aware Compiling and Scheduling
M. Kandemir, Pennsylvania State University
I. Kadayif, Canakkale Onsekiz Mart University
G. Chen, Pennsylvania State University
pp. 98-103
Manish Verma, University of Dortmund
Lars Wehmeyer, University of Dortmund
Peter Marwedel, University of Dortmund
pp. 104-109
Session A4: System-Level Design Space Exploration for Hardware-Software Partitioning and Platform Instantiation
Sudarshan Banerjee, University of California at Irvine
Nikil Dutt, University of California at Irvine
pp. 122-127
Alexander Maxiaguine, ETH Z?urich
Yongxin Zhu, National University of Singapore
Samarjit Chakraborty, National University of Singapore
Weng-Fai Wong, National University of Singapore
pp. 128-133
Session B4: Estimation and Design Techniques for Energy-Efficient Memory Systems
Chin-Hsien Wu, National Taiwan University
Tei-Wei Kuo, National Taiwan University
Chia-Lin Yang, National Taiwan University
pp. 134-139
Rajeev Krishna, University of Michigan
Scott Mahlke, University of Michigan
Todd Austin, University of Michigan
pp. 140-145
Mahesh Mamidipaka, University of California at Irvine
Kamal Khouri, Freescale/Motorola Inc.
Nikil Dutt, University of California at Irvine
Magdy Abadir, Freescale/Motorola Inc.
pp. 146-151
Session A5: Advances in Hardware/Software Co-Simulation Techniques
Luca Formaggio, Università di Verona
Franco Fummi, Università di Verona
Graziano Pravadelli, Università di Verona
pp. 152-157
Shinya Honda, Toyohashi University of Technology
Takayuki Wakabayashi, Toyohashi University of Technology
Hiroyuki Tomiyama, Nagoya University
Hiroaki Takada, Nagoya University
pp. 158-163
Zhengting He, University of Texas-Austin
Aloysius Mok, University of Texas-Austin
pp. 164-169
Session B5: NoC Design and Optimisation
Giuseppe Ascia, University of Catania
Vincenzo Catania, University of Catania
Maurizio Palesi, University of Catania
pp. 182-187
Session A6: Software and Hardware Techniques for Performance Optimisation of Embedded Applications
Aviral Shrivastava, University of California at Irvine
Eugene Earlie, Intel Labs
Nikil Dutt, University of California at Irvine
Alex Nicolau, Intel Labs
pp. 194-199
Jaehwan Lee, Georgia Institute of Technology
Vincent John Mooney III, Georgia Institute of Technology
pp. 200-205
Session B6: Special Session
Session A7: New Techniques for Security and Reliability Enhancement in Embedded Systems
G. Chen, Pennsylvania State University
M. Kandemir, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
A. Sivasubramaniam, Pennsylvania State University
M. J. Irwin, Pennsylvania State University
pp. 230-235
Session B7: On-Chip Communication Architectures: Analysis and Optimisation
Sudeep Pasricha, University of California at Irvine
Nikil Dutt, University of California at Irvine
Mohamed Ben-Romdhane, Conexant Systems Inc.
pp. 242-247
Sungchan Kim, Seoul National University
Chaeseok Im, Seoul National University
Soonhoi Ha, Seoul National University
pp. 248-253
Panel 2
Peter Marwedel, University of Dortmund + ICD
Daniel Gajski, University of California at Irvine
Erwin De Kock, Philips
Hugo De Man, K.U. Leuven + IMEC
Peter Marwedel, University of Dortmund + ICD
Mariagiovanna Sami, Politechnico di Milano
pp. 254-255
Author Index
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