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2010 10th IEEE International Conference on Computer and Information Technology
Network Main Memory Architecture for NoC-Based Chips
Bradford, West Yorkshire, UK
June 29-July 01
ISBN: 978-0-7695-4108-2
| ASCII Text | x | ||
| Xingsheng Tang, Binbin Wu, Tianzhou Chen, Wei Hu, Jiexiang Kang, Zhenwei Zheng, "Network Main Memory Architecture for NoC-Based Chips," Computer and Information Technology, International Conference on, pp. 2516-2523, 2010 10th IEEE International Conference on Computer and Information Technology, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/CIT.2010.429, author = {Xingsheng Tang and Binbin Wu and Tianzhou Chen and Wei Hu and Jiexiang Kang and Zhenwei Zheng}, title = {Network Main Memory Architecture for NoC-Based Chips}, journal ={Computer and Information Technology, International Conference on}, volume = {0}, year = {2010}, isbn = {978-0-7695-4108-2}, pages = {2516-2523}, doi = {http://doi.ieeecomputersociety.org/10.1109/CIT.2010.429}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Computer and Information Technology, International Conference on TI - Network Main Memory Architecture for NoC-Based Chips SN - 978-0-7695-4108-2 SP2516 EP2523 A1 - Xingsheng Tang, A1 - Binbin Wu, A1 - Tianzhou Chen, A1 - Wei Hu, A1 - Jiexiang Kang, A1 - Zhenwei Zheng, PY - 2010 KW - network on chip KW - main memory KW - memory bandwidth VL - 0 JA - Computer and Information Technology, International Conference on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CIT.2010.429
Network on Chip (NoC) is considered to be the best candidate for future on-chip communication; however, with the increase in the number of on-chip processors, the simultaneous memory accesses of these processors can cause serious main memory bottleneck problem. In this study, we have proposed the concept of Network Main Memory (NMM). NMM has distributed network architecture for main memory and multicommunication channels to NoC chips, which can overcome the main memory bottleneck problem. When compared with traditional memory, the bandwidth of NMM can be sufficiently used owing to the network architecture, and it is convenient to increase the memory bandwidth. Our experimental results on simulator show that our NMM can provide better traffic for NoCs. In addition, management of NMM as well as the software model for NoC chips and NMM have also been discussed.
Index Terms:
network on chip, main memory, memory bandwidth
Citation:
Xingsheng Tang, Binbin Wu, Tianzhou Chen, Wei Hu, Jiexiang Kang, Zhenwei Zheng, "Network Main Memory Architecture for NoC-Based Chips," cit, pp.2516-2523, 2010 10th IEEE International Conference on Computer and Information Technology, 2010
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