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2011 Seventh International Conference on Computational Intelligence and Security
Global Prefetcher Aggressiveness Control for Chip-Multiprocessor
Sanya, Hainan China
December 03-December 04
ISBN: 978-0-7695-4584-4
ASCII Text
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Limin Han, Deyuan Gao, Xiaoya Fan, Liwen Shi, Jianfeng An, "Global Prefetcher Aggressiveness Control for Chip-Multiprocessor," 2012 Eighth International Conference on Computational Intelligence and Security, pp. 273-277, 2011 Seventh International Conference on Computational Intelligence and Security, 2011.
 
 
BibTex
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@article{ 10.1109/CIS.2011.68,
author = {Limin Han and Deyuan Gao and Xiaoya Fan and Liwen Shi and Jianfeng An},
title = {Global Prefetcher Aggressiveness Control for Chip-Multiprocessor},
journal ={2012 Eighth International Conference on Computational Intelligence and Security},
volume = {0},
year = {2011},
isbn = {978-0-7695-4584-4},
pages = {273-277},
doi = {http://doi.ieeecomputersociety.org/10.1109/CIS.2011.68},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - 2012 Eighth International Conference on Computational Intelligence and Security
TI - Global Prefetcher Aggressiveness Control for Chip-Multiprocessor
SN - 978-0-7695-4584-4
SP273
EP277
A1 - Limin Han,
A1 - Deyuan Gao,
A1 - Xiaoya Fan,
A1 - Liwen Shi,
A1 - Jianfeng An,
PY - 2011
KW - global control
KW - hardware prefetcher
KW - shared memory
KW - Last level cache
KW - CMP
VL - 0
JA - 2012 Eighth International Conference on Computational Intelligence and Security
ER -
 
Aggressive prefetching may cause much inter-core interference and lead to large performance in shared memory CMP systems. The paper aims at improving system performance and making prefetching effective. We study prefetching-caused inter-core interference of CMP system and propose a Global Prefetcher Aggressiveness Control Scheme (GPACS) to reduce useless and aggressive prefetches. It controls the aggressiveness of multiple hardware prefetchers of different cores in CMP using a global control mechanism. The key idea of the scheme is taking into account both shared last level cache and memory queue prefetch-caused inter-core interference for determining the aggressiveness of each core's prefetcher. Our evaluations show that GPACS significantly improves the performance of prefetching with a low-hardware cost and makes it effective in multi-core environments.
Index Terms:
global control, hardware prefetcher, shared memory, Last level cache, CMP
Citation:
Limin Han, Deyuan Gao, Xiaoya Fan, Liwen Shi, Jianfeng An, "Global Prefetcher Aggressiveness Control for Chip-Multiprocessor," cis, pp.273-277, 2011 Seventh International Conference on Computational Intelligence and Security, 2011
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