CSDL - Proceedings C

Message from the Program Chair (PDF)

pp. x-x

Committees (PDF)

pp. xi-xiii

Reviewers (PDF)

pp. xiv-xiv

Corporate Sponsors (PDF)

pp. xv-xv

3rd Workshop on Optimizations for DSP and Embedded Systems (ODES)

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3rd Workshop on Managed Runtime Environments (MRE-3)

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4th Workshop on EPIC Architectures and Compiler Technology (EPIC-4)

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Tutorial on Software Dynamic Translation: Challenges, Approaches and Applications

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Keynote 1

Virtual Machine Learning: Thinking like a Computer Architect (PDF)

Michael Hind, IBM T. J. Watson Research Center

pp. 11-11

Session 1: Virtual Machine Technologies

Context Threading: A Flexible and Efficient Dispatch Technique for Virtual Machine Interpreters (Abstract)

Marc Berndl, University of Toronto

Benjamin Vitale, University of Toronto

Mathew Zaleski, University of Toronto

Angela Demke Brown, University of Toronto

pp. 15-26

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Automatically Reducing Repetitive Synchronization with a Just-in-Time Compiler for Java (Abstract)

Mark Stoodley, Toronto Lab, IBM Canada Ltd.

Vijay Sundaresan, Toronto Lab, IBM Canada Ltd.

pp. 27-36

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Compile-Time Concurrent Marking Write Barrier Removal (Abstract)

V. Krishna Nandivada, UCLA Computer Science Dept.

David Detlefs, Sun Microsystems Inc., Burlington, MA

pp. 37-48

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Session 2: Dynamic Optimization

Collecting and Exploiting High-Accuracy Call Graph Profiles in Virtual Machines (Abstract)

Matthew Arnold, IBM T.J. Watson Research Center

David Grove, IBM T.J. Watson Research Center

pp. 51-62

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Effective Adaptive Computing Environment Management via Dynamic Optimization (Abstract)

Shiwen Hu, The University of Texas at Austin

Madhavi Valluri, The University of Texas at Austin

Lizy Kurian John, The University of Texas at Austin

pp. 63-73

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Maintaining Consistency and Bounding Capacity of Software Code Caches (Abstract)

Derek Bruening, MIT Computer Science and Artificial Intelligence Laboratory and Determina Corporation

Saman Amarasinghe, MIT Computer Science and Artificial Intelligence Laboratory and Determina Corporation

pp. 74-85

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Performance of Runtime Optimization on BLAST (Abstract)

Abhinav Das, University of Minnesota

Jiwei Lu, University of Minnesota

Howard Chen, University of Minnesota

Jinpyo Kim, University of Minnesota

Pen-Chung Yew, University of Minnesota

Wei-Chung Hsu, University of Minnesota

Dong-Yuan Chen, Intel Corporation

pp. 86-96

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Session 3: Searching the Optimization Space

Optimizing Sorting with Genetic Algorithms (Abstract)

Xiaoming Li, University of Illinois at Urbana-Champaign

Mar?a Jes? Garzar?, University of Illinois at Urbana-Champaign

David Padua, University of Illinois at Urbana-Champaign

pp. 99-110

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Combining Models and Guided Empirical Search to Optimize for Multiple Levels of the Memory Hierarchy (Abstract)

Chun Chen, University of Southern California, Marina del Rey

Jacqueline Chame, University of Southern California, Marina del Rey

Mary Hall, University of Southern California, Marina del Rey

pp. 111-122

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Predicting Unroll Factors Using Supervised Classification (Abstract)

Mark Stephenson, Massachusetts Institute of Technology, Cambridge

Saman Amarasinghe, Massachusetts Institute of Technology, Cambridge

pp. 123-134

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Keynote 2

Multicores from the Compiler's Perspective: A Blessing or a Curse? (PDF)

Saman Amarasinghe, Massachusetts Institute of Technology, CTO, Determina Corporation

pp. 137-137

Session 4: Optimizing Embedded Systems

Optimizing Address Code Generation for Array-Intensive DSP Applications (Abstract)

Guilin Chen, The Pennsylvania State University, University Park

Mahmut Kandemir, The Pennsylvania State University, University Park

pp. 141-152

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Efficient SIMD Code Generation for Runtime Alignment and Length Conversion (Abstract)

Peng Wu, IBM T.J. Watson Research Center, Yorktown Heights, NY

Alexandre E. Eichenberger, IBM T.J. Watson Research Center, Yorktown Heights, NY

Amy Wang, IBM Toronto Laboratory, Markham, Ontario, Canada

pp. 153-164

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Superword-Level Parallelism in the Presence of Control Flow (Abstract)

Jaewook Shin, University of Southern California, Marina del Rey

Mary Hall, University of Southern California, Marina del Rey

Jacqueline Chame, University of Southern California, Marina del Rey

pp. 165-175

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Session 5: Code Profiling and Optimizations for Embedded Systems

Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache (Abstract)

Rajiv A. Ravindran, University of Michigan, Ann Arbor

Pracheeti D. Nagarkar, University of Michigan, Ann Arbor

Ganesh S. Dasika, University of Michigan, Ann Arbor

Eric D. Marsman, University of Michigan, Ann Arbor

Robert M. Senger, University of Michigan, Ann Arbor

Scott A. Mahlke, University of Michigan, Ann Arbor

Richard B. Brown, University of Utah, Salt Lake City

pp. 179-190

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Phase-Aware Remote Profiling (Abstract)

Priya Nagpurkar, University of California, Santa Barbara

Chandra Krintz, University of California, Santa Barbara

Timothy Sherwood, University of California, Santa Barbara

pp. 191-202

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Session 6: Profiling and Trace Compression

Practical Path Profiling for Dynamic Optimizers (Abstract)

Michael D. Bond, University of Texas at Austin

Kathryn S. McKinley, University of Texas at Austin

pp. 205-216

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A Programmable Hardware Path Profiler (Abstract)

Kapil Vaswani, Indian Institute of Science, Bangalore

Matthew J. Thazhuthaveetil, Indian Institute of Science, Bangalore

Y. N. Srikant, Indian Institute of Science, Bangalore

pp. 217-228

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Automatic Generation of High-Performance Trace Compressors (Abstract)

Martin Burtscher, Cornell University

Nana B. Sam, Cornell University

pp. 229-240

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Session 7: Security and Reliability

SWIFT: Software Implemented Fault Tolerance (Abstract)

George A. Reis, Princeton University, NJ

Jonathan Chang, Princeton University, NJ

Neil Vachharajani, Princeton University, NJ

Ram Rangan, Princeton University, NJ

David I. August, Princeton University, NJ

pp. 243-254

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Building Intrusion-Tolerant Secure Software (Abstract)

Tao Zhang, Georgia Institute of Technology, Atlanta, GA

Xiaotong Zhuang, Georgia Institute of Technology, Atlanta, GA

Santosh Pande, Georgia Institute of Technology, Atlanta, GA

pp. 255-266

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Session 8: Pointer Analysis and Register Allocation

A Progressive Register Allocator for Irregular Architectures (Abstract)

David Koes, Carnegie Mellon University

Seth Copen Goldstein, Carnegie Mellon University

pp. 269-280

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A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion (Abstract)

Xiaoru Dai, University of Minnesota, Minneapolis

Antonia Zhai, University of Minnesota, Minneapolis

Wei-Chung Hsu, University of Minnesota, Minneapolis

Pen-Chung Yew, University of Minnesota, Minneapolis

pp. 280-290

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Practical and Accurate Low-Level Pointer Analysis (Abstract)

Bolei Guo, Princeton University

Matthew J. Bridges, Princeton University

Spyridon Triantafyllis, Princeton University

Guilherme Ottoni, Princeton University

Easwaran Raman, Princeton University

David I. August, Princeton University

pp. 291-302

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Session 9: Software Speculation

Reactive Techniques for Controlling Software Speculation (Abstract)

Craig Zilles, University of Illinois at Urbana-Champaign

Naveen Neelakantam, University of Illinois at Urbana-Champaign

pp. 305-316

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A Model-Based Framework: An Approach for Profit-Driven Optimization (Abstract)

Min Zhao, University of Pittsburgh

Bruce R. Childers, University of Pittsburgh

Mary Lou Soffa, University of Virginia

pp. 317-327

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Sentinel PRE: Hoisting beyond Exception Dependency with Dynamic Deoptimization (Abstract)

Rei Odaira, University of Tokyo, Japan

Kei Hiraki, University of Tokyo, Japan

pp. 328-338

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Author Index (PDF)

pp. 339-339