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International Symposium on Code Generation and Optimization (CGO'04)
San Jose, California
March 20-March 24
ISBN: 0-7695-2102-9
Table of Contents
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2nd Workshop on Optimizations for DSP and Embedded Systems (ODES2)
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2nd Workshop on Managed Runtime Environments (MRE'04)
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Workshop on Software for Processor-In-Memory Based Parallel Systems
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3rd Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology (EPIC-3)
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Tutorials
Software Instrumentation and Hardware Profiling for Itanium Linux
Dynamic Compilation and Adaptive Optimization in Virtual Machines
Keynotes
Evolving the Next Generation of Compilers
Is Performance Research Done?
Session 1: Optimizing Memory Performance
Chi-Keung Luk, Intel Corporation
Robert Muth, Intel Corporation
Harish Patil, Intel Corporation
Robert Cohn, Intel Corporation
Geoff Lowney, Intel Corporation
pp. 15
Dongkeun Kim, Intel Corporation; University of Maryland at College Park
Steve Shih-wei Liao, Intel Corporation
Perry H. Wang, Intel Corporation
Juan del Cuvillo, Intel Corporation
Xinmin Tian, Intel Corporation
Xiang Zou, Intel Corporation
Hong Wang, Intel Corporation
Donald Yeung, University of Maryland at College Park
Milind Girkar, Intel Corporation
John P. Shen, Intel Corporation
pp. 27
Antonia Zhai, Carnegie Mellon University, Pittsburgh, PA
Christopher B. Colohan, Carnegie Mellon University, Pittsburgh, PA
J. Gregory Steffan, University of Toronto, Ontario
Todd C. Mowry, Carnegie Mellon University, Pittsburgh, PA
pp. 39
Session 2: New Frameworks
Michael Dupr?, LRI, Paris South University, France
Nathalie Drach, LRI, Paris South University, France
Olivier Temam, LRI, Paris South University, France
pp. 53
Sungdo Moon, Hewlett-Packard Company, Cupertino, CA
Xinliang D. Li, Hewlett-Packard Company, Cupertino, CA
Robert Hundt, Hewlett-Packard Company, Cupertino, CA
Dhruva R. Chakrabarti, Hewlett-Packard Company, Cupertino, CA
Luis A. Lozano, Hewlett-Packard Company, Cupertino, CA
Uma Srinivasan, Hewlett-Packard Company, Cupertino, CA
Shin-Ming Liu, Hewlett-Packard Company, Cupertino, CA
pp. 65
Chris Lattner, University of Illinois at Urbana-Champaign
Vikram Adve, University of Illinois at Urbana-Champaign
pp. 75
Session 3: More Memory Performance
Ali-Reza Adl-Tabatabai, Intel Corporation
Jay Bharadwaj, Intel Corporation
Michal Cierniak, Microsoft Corporation
Marsha Eng, Intel Corporation
Jesse Fang, Intel Corporation
Brian T. Lewis, Intel Corporation
Brian R. Murphy, Intel Corporation
James M. Stichnoth, Intel Corporation
pp. 100
Xiaoming Li, University of Illinois at Urbana-Champaign
Mar?a Jes? Garzar?, University of Illinois at Urbana-Champaign
David Padua, University of Illinois at Urbana-Champaign
pp. 111
Session 4: Optimizing for Energy Efficiency
Ramon Canal, Universitat Polit?cnica de Catalunya
Antonio Gonz?lez, Universitat Polit?cnica de Catalunya
James E. Smith, University of Wisconsin-Madison
pp. 125
Yoav Almog, Microprocessor Research, Intel Labs, Haifa, Israel
Roni Rosner, Microprocessor Research, Intel Labs, Haifa, Israel
Naftali Schwartz, Microprocessor Research, Intel Labs, Haifa, Israel
Ari Schmorak, Microprocessor Research, Intel Labs, Haifa, Israel
pp. 137
Session 5: Loop Scheduling
Mikhail Smelyanskiy, University of Michigan, Ann Arbor
Scott Mahlke, University of Michigan, Ann Arbor
Edward S. Davidson, University of Michigan, Ann Arbor
pp. 151
Hongbo Rong, University of Delaware, Newark
Zhizhong Tang, Tsinghua University, Beijing, China
R. Govindarajan, Indian Institute of Science, Bangalore, India
Alban Douillet, University of Delaware, Newark
Guang R. Gao, University of Delaware, Newark
pp. 163
Hongbo Rong, University of Delaware, Newark
Alban Douillet, University of Delaware, Newark
R. Govindarajan, Indian Institute of Science, Bangalore, India
Guang R. Gao, University of Delaware, Newark
pp. 175
Session 6: Instruction Scheduling
Manjunath Kudlur, University of Michigan, Ann Arbor
Kevin Fan, University of Michigan, Ann Arbor
Michael Chu, University of Michigan, Ann Arbor
Rajiv Ravindran, University of Michigan, Ann Arbor
Nathan Clark, University of Michigan, Ann Arbor
Scott Mahlke, University of Michigan, Ann Arbor
pp. 201
Shiliang Hu, University of Wisconsin - Madison
James E. Smith, University of Wisconsin - Madison
pp. 213
Session 7: Code Profiling
Youfeng Wu, Intel Corporation
Mauricio Breternitz, Intel Corporation
Justin Quek, University of Illinois, Urbana-Champaign
Orna Etzion, Intel Corporation
Jesse Fang, Intel Corporation
pp. 227
Rahul Joshi, University of Illinois at Urbana-Champaign
Michael D. Bond, University of Texas at Austin
Craig Zilles, University of Illinois at Urbana-Champaign
pp. 239
Session 8: Compile-time Optimization
F. Rastello, LIP, ?cole Normale Sup?rieure de Lyon, France
F. de Ferri?re, STMicroelectronics, France
C. Guillon, STMicroelectronics, France
pp. 265
Yonghua Ding, Purdue University, West Lafayette, Indiana
Zhiyuan Li, Purdue University, West Lafayette, Indiana
pp. 279
Session 9: Memory Profiling and Data Layout
Byoungro So, IBM T. J. Watson Research Center, Yorktown Heights, NY
Mary W. Hall, University of Southern California, Marina del Rey, CA
Heidi E. Ziegler, University of Southern California, Marina del Rey, CA
pp. 291
Vlad-Mihai Panait, Politehnica University of Bucharest, Romania
Amit Sasturkar, Stony Brook University, NY
Weng-Fai Wong, National University of Singapore
pp. 303
Qiang Wu, Princeton University, NJ
Artem Pyatakov, Princeton University, NJ
Alexey Spiridonov, Princeton University, NJ
Easwaran Raman, Princeton University, NJ
Douglas W. Clark, Princeton University, NJ
David I. August, Princeton University, NJ
pp. 315
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