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San Jose, California
Mar. 20, 2004 to Mar. 24, 2004
ISBN: 0-7695-2102-9
pp: 201
Manjunath Kudlur , University of Michigan, Ann Arbor
Kevin Fan , University of Michigan, Ann Arbor
Michael Chu , University of Michigan, Ann Arbor
Rajiv Ravindran , University of Michigan, Ann Arbor
Nathan Clark , University of Michigan, Ann Arbor
Scott Mahlke , University of Michigan, Ann Arbor
ABSTRACT
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing the hardware to suit an application. A central problem is creating compilers that are capable of dealing with the heterogeneous and non-uniform hardware created by the customization process. The processor datapath provides an effective area to customize, but specialized datapaths often have non-uniform connectivity between the function units, making the effective latency of a function unit dependent on the consuming operation. Traditional instruction schedulers break down in this environment due to their locally greedy nature of binding the best choice for a single operation even though that choice may be poor due to a lack of communication paths. To effectively schedule with non-uniform connectivity, we propose a foresighted latency-aware scheduling heuristic (FLASH) that performs lookahead across future scheduling steps to estimate the effects of a potential binding. FLASH combines a set of lookahead heuristics to achieve effective foresight with low compile-time overhead.
INDEX TERMS
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CITATION
Manjunath Kudlur, Kevin Fan, Michael Chu, Rajiv Ravindran, Nathan Clark, Scott Mahlke, "FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths", CGO, 2004, Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO) 2004, pp. 201, doi:10.1109/CGO.2004.1281675
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