[Front cover]

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

[Copyright notice] (PDF)

pp. iv

Table of contents (PDF)

pp. v-xi

Message from the General Chair (PDF)

pp. xii

Message from the Program Co-chairs (PDF)

pp. xiii

Organizing Committee (PDF)

pp. xiv-xvi

list-reviewer (PDF)

pp. xvii

Special Panel Session (PDF)

pp. xviii

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level (Abstract)

Hans-Joachim Wunderlich

pp. 3-8

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Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-sampling (Abstract)

Hyun Choi

Abhijit Chatterjee

pp. 9-14

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FSimGP^2: An Efficient Fault Simulator with GPGPU (Abstract)

Min Li

pp. 15-20

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A Quasi-best Random Testing (Abstract)

Shiyi Xu

Peng Xu

pp. 21-26

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Testing of Low-Cost Digital Microfluidic Biochips with Non-regular Array Layouts (Abstract)

Yang Zhao

pp. 27-32

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Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits (Abstract)

Dipak K. Kole

Hafizur Rahaman

Debesh K. Das

Bhargab B. Bhattacharya

pp. 33-38

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On Determining the Real Output Xs by SAT-Based Reasoning (Abstract)

Melanie Elm

Michael A. Kochte

Hans-Joachim Wunderlich

pp. 39-44

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On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing (Abstract)

pp. 45-48

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Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment (Abstract)

pp. 53-56

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Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs (Abstract)

Saparya Krishnamoorthy

Loganathan Lingappan

pp. 59-64

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A Reliability Model for Object-Oriented Software (Abstract)

Peng Xu

Shiyi Xu

pp. 65-70

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A New Approach to Generating High Quality Test Cases (Abstract)

Pan Liu

Huaikou Miao

pp. 71-76

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A Study on Software Reliability Prediction Based on Transduction Inference (Abstract)

Jungang Lou

Jianhui Jiang

Chunyan Shuai

Ying Wu

pp. 77-80

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Formula-Oriented Compositional Minimization in Model Checking (Abstract)

pp. 81-84

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Variation-Aware Fault Modeling (Abstract)

Hans-Joachim Wunderlich

pp. 87-93

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Diagnosis of Multiple Physical Defects Using Logic Fault Models (Abstract)

pp. 94-99

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A Memory Fault Simulator for Radiation-Induced Effects in SRAMs (Abstract)

P. Rech

pp. 100-105

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On Soft Error Immunity of Sequential Circuits (Abstract)

Dan Zhu

Tun Li

Si-kun Li

pp. 106-110

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Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem (Abstract)

Debasis Mitra

Sarmishtha Ghoshal

Hafizur Rahaman

Bhargab B. Bhattacharya

pp. 111-116

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P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework (Abstract)

pp. 117-120

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A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces (Abstract)

Hyunjin Kim

Jacob A. Abraham

pp. 123-128

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A Complete Logic BIST Technology with No Storage Requirement (Abstract)

Wei-Cheng Lien

Kuen-Jong Lee

pp. 129-134

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Built-In Self-Test for Capacitive MEMS Using a Charge Control Technique (Abstract)

pp. 135-140

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Xrysovalantis Kavousianos

Defect Coverage-Driven Window-Based Test Compression (Abstract)

Emmanouil Kalligeros

Vasileios Tenentes

pp. 141-146

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Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST (Abstract)

pp. 147-152

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Parallel LFSR Reseeding with Selection Register for Mixed-Mode BIST (Abstract)

Piyanart Kongtim

Taweesak Reungpeerakul

pp. 153-158

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Efficient Embedding of Deterministic Test Data (Abstract)

pp. 159-162

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Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code (Abstract)

pp. 163-166

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On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter (Abstract)

Jianjun Yu

Fa Foster Dai

pp. 167-170

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Pattern Encodability Enhancements for Test Stimulus Decompressors (Abstract)

pp. 173-178

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High Performance Compaction for Test Responses with Many Unknowns (Abstract)

pp. 179-184

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Design-for-Test of Digitally-Assisted Analog IPs for Automotive SoCs (Abstract)

Yizi Xing

Liquan Fang

pp. 185-191

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Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method (Abstract)

Jing Ye

Xiaolin Zhang

Yu Hu

Xiaowei Li

pp. 192-197

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D-Scale: A Scalable System-Level Dependable Method for MPSoCs (Abstract)

pp. 198-205

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Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits (Abstract)

pp. 206-211

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XOR-Based Response Compactor Adaptive to X-Density Variation (Abstract)

Samah Mohamed Saeed

Ozgur Sinanoglu

pp. 212-217

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DFT + DFD: An Integrated Method for Design for Testability and Diagnosability (Abstract)

Nikhil Rahagude

Maheshwar Chandrasekar

pp. 218-223

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Accelerating Strategy for Functional Test of NoC Communication Fabric (Abstract)

pp. 224-227

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HYPERA: High-Yield Performance-Efficient Redundancy Analysis (Abstract)

pp. 231-236

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A Comprehensive System-on-Chip Logic Diagnosis (Abstract)

pp. 237-242

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On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation (Abstract)

Xiao Liu

Qiang Xu

pp. 243-248

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HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC (Abstract)

Mohammad Mirza-Aghatabar

Melvin A. Breuer

Sandeep K. Gupta

pp. 249-254

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Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking (Abstract)

Wu-Tung Cheng

Yu Huang

pp. 255-260

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Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure (Abstract)

Chih-Yun Pai

Katherine Shu-Min Li

pp. 261-266

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At-speed Test of High-Speed DUT Using Built-Off Test Interface (Abstract)

pp. 269-274

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Rapid Radio Frequency Amplitude and Phase Distortion Measurement Using Amplitude Modulated Stimulus (Abstract)

pp. 277-282

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Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional Signatures (Abstract)

S. Sen

H. Choi

pp. 283-288

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The Test Ability of an Adaptive Pulse Wave for ADC Testing (Abstract)

Xiaoqin Sheng

Hans G. Kerkhoff

pp. 289-294

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Haralampos-G. Stratigopoulos

Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation (Abstract)

Ke Huang

Salvador Mir

pp. 295-298

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Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test (Abstract)

pp. 301-306

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Circuit Topology-Based Test Pattern Generation for Small-Delay Defects (Abstract)

Sandeep Kumar Goel

Mahmut Yilmaz

Ke Peng

Mohammad Tehranipoor

pp. 307-312

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Seed Ordering and Selection for High Quality Delay Test (Abstract)

pp. 313-318

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An Efficient Algorithm for Finding a Universal Set of Testable Long Paths (Abstract)

Tao Lv

pp. 319-324

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Distinguishing Resistive Small Delay Defects from Random Parameter Variations (Abstract)

Xi Qian

Adit D. Singh

pp. 325-330

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A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection (Abstract)

Ke Peng

Mahmut Yilmaz

Mohammad Tehranipoor

pp. 331-336

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Thermal Safe High Level Test Synthesis for Hierarchical Testability (Abstract)

Tung-Hua Yeh

Sying-Jyan Wang

pp. 337-342

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A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit (Abstract)

pp. 343-348

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On Bias in Transition Coverage of Test Sets for Path Delay Faults (Abstract)

Irith Pomeranz

Sudhakar M. Reddy

pp. 349-352

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Adaptive Low Shift Power Test Pattern Generator for Logic BIST (Abstract)

Xijiang Lin

Janusz Rajski

pp. 355-360

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Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing (Abstract)

pp. 361-366

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Modified Scan Flip-Flop for Low Power Testing (Abstract)

Satdev

pp. 367-370

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Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power (Abstract)

pp. 371-374

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A Test Integration Methodology for 3D Integrated Circuits (Abstract)

pp. 377-382

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Performance Characterization of TSV in 3D IC via Sensitivity Analysis (Abstract)

pp. 389-394

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Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation (Abstract)

pp. 395-398

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Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing (Abstract)

Krishna Kumar S.

Kaundinya S.

Santanu Chattopadhyay

pp. 401-406

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New Microcode's Generation Technique for Programmable Memory Built-In Self Test (Abstract)

pp. 407-412

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Software-Based Self-Testing of Processors Using Expanded Instructions (Abstract)

pp. 415-420

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Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures (Abstract)

Hongxia Fang

Zhiyuan Wang

Xinli Gu

pp. 421-428

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Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test (Abstract)

Zhaobo Zhang

Zhanglei Wang

Xinli Gu

pp. 429-432

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Test Cost Analysis for 3D Die-to-Wafer Stacking (Abstract)

pp. 435-441

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Mining Complex Boolean Expressions for Sequential Equivalence Checking (Abstract)

Neha Goel

Narendran Ramakrishnan

Mohammed J. Zaki

pp. 442-447

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On-the-Fly Reduction of Stimuli for Functional Verification (Abstract)

Qi Guo

pp. 448-454

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Test Time Analysis for IEEE P1687 (Abstract)

Farrokh Ghani Zadegan

pp. 455-460

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Author Index (PDF)

pp. 461-463

[Publisher's information] (PDF)

pp. 464