CSDL - Proceedings A

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-xi

Foreword (PDF)

pp. xii

Organizing Committee (PDF)

pp. xiii

Steering Committee (PDF)

pp. xiv

Program Committee (PDF)

pp. xv-xvi

Reviewers (PDF)

pp. xvii

Tutorials (PDF)

pp. xviii-xix

Keynotes (PDF)

pp. xx-xxiii

Best Paper Award of ATS 2008 (PDF)

pp. xxiv

Call for Papers of ATS 2010 (PDF)

pp. xxv

CA Based Built-In Self-Test Structure for SoC (Abstract)

Sukanta Das

Biplab K. Sikdar

pp. 3-8

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A Random Jitter RMS Estimation Technique for BIST Applications (Abstract)

pp. 9-14

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A Novel Seed Selection Algorithm for Test Time Reduction in BIST (Abstract)

Rupsa Chakraborty

Dipanwita Roy Chowdhury

pp. 15-20

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Logic BIST Architecture for System-Level Test and Diagnosis (Abstract)

pp. 21-26

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Fault Diagnosis under Transparent-Scan (Abstract)

Irith Pomeranz

Sudhakar M. Reddy

pp. 29-34

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Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns (Abstract)

pp. 35-40

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On Improving Diagnostic Test Generation for Scan Chain Failures (Abstract)

pp. 41-46

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On Scan Chain Diagnosis for Intermittent Faults (Abstract)

pp. 47-54

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Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique (Abstract)

pp. 57-62

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Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients (Abstract)

pp. 63-68

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Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs (Abstract)

S. Kook

Le Jin

pp. 69-74

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Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits (Abstract)

pp. 75-80

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Scan Compression Implementation in Industrial Design - Case Study (Abstract)

Dragon Hsu

Ron Press

pp. 83-84

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Calibration as a Functional Test: An ADC Case Study (Abstract)

pp. 85-86

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Customized Algorithms for High Performance Memory Test in Advanced Technology Node (Abstract)

pp. 87-89

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A Practical DFT Approach for Complex Low Power Designs (Abstract)

Augusli Kifli

Y.W. Chen

Y.W. Tsay

K.C. Wu

pp. 90-91

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DFT Challenges in Next Generation Multi-media IP (Abstract)

pp. 92-93

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Yield Ramp up by Scan Chain Diagnosis (Abstract)

Feng-Ming Kuo

Yuan-Shih Chhen

pp. 94-95

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CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing (Abstract)

X. Wen

H. Sone

M. Aso

pp. 99-104

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New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology (Abstract)

pp. 105-110

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Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing (Abstract)

pp. 111-116

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Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder (Abstract)

Ming Gao

Kwang-Ting Cheng

pp. 119-124

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A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems (Abstract)

pp. 125-130

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Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug (Abstract)

Sandesh Prabhakar

Michael Hsiao

pp. 131-136

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A Post-Silicon Debug Support Using High-Level Design Description (Abstract)

pp. 137-142

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A Low Overhead On-Chip Path Delay Measurement Circuit (Abstract)

pp. 145-150

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An Adaptive Test for Parametric Faults Based on Statistical Timing Information (Abstract)

pp. 151-156

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A Delay Measurement Technique Using Signature Registers (Abstract)

pp. 157-162

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Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test (Abstract)

pp. 163-168

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A Practical Approach to Threshold Test Generation for Error Tolerant Circuits (Abstract)

pp. 171-176

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Speeding up SAT-Based ATPG Using Dynamic Clause Activation (Abstract)

pp. 177-182

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N-distinguishing Tests for Enhanced Defect Diagnosis (Abstract)

pp. 183-186

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Dynamic Compaction in SAT-Based ATPG (Abstract)

pp. 187-190

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SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement (Abstract)

Mohammad Mirza-Aghatabar

Melvin A. Breuer

Sandeep K. Gupta

pp. 193-199

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Transaction Level Modeling and Design Space Exploration for SOC Test Architectures (Abstract)

pp. 200-205

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Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors (Abstract)

pp. 206-211

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Is Low Power Testing Necessary? What does the Test Industry Truly Need? (Abstract)

Anis Uzzaman

pp. 215-216

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A Scalable Scan Architecture for Godson-3 Multicore Microprocessor (Abstract)

Hui Liu

Da Wang

pp. 219-224

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Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time (Abstract)

Michael S. Hsiao

Mainak Banga

pp. 225-230

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Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint (Abstract)

pp. 231-236

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Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing (Abstract)

pp. 237-240

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BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search (Abstract)

Vishwanath Natarajan

Shyam Kumar Devarakond

Shreyas Sen

Abhijit Chatterjee

pp. 243-248

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Self-Calibrating Embedded RF Down-Conversion Mixers (Abstract)

pp. 249-254

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A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis (Abstract)

pp. 255-260

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Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE (Abstract)

pp. 261-266

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IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency (Abstract)

pp. 269-274

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Multiple-Core under Test Architecture for HOY Wireless Testing Platform (Abstract)

pp. 275-280

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Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies (Abstract)

Chunhua Yao

Kewal K. Saluja

Parameswaran Ramanathan

pp. 281-286

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Test Integration for SOC Supporting Very Low-Cost Testers (Abstract)

pp. 287-292

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Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs? (Abstract)

Krishna Chakravadhanula

pp. 295-300

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New Class of Tests for Open Faults with Considering Adjacent Lines (Abstract)

pp. 301-306

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Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption (Abstract)

Subhadip Kundu

Krishna Kumar S.

Santanu Chattopadhyay

pp. 307-312

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Deterministic Algorithms for ATPG under Leakage Constraints (Abstract)

Görschwin Fey

pp. 313-316

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Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power (Abstract)

Jun Liu

Yinhe Han

Xiaowei Li

pp. 319-324

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A Multi-dimensional Pattern Run-Length Method for Test Data Compression (Abstract)

pp. 325-330

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Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage (Abstract)

Hongxia Fang

Krishnendu Chakrabarty

Rubin Parekhji

pp. 331-336

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Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive? (Abstract)

Said Hamdioui

pp. 339

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A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities (Abstract)

Ying-Yen Chen

Jing-Jia Liou

pp. 343-348

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Bridging Fault Diagnosis to Identify the Layer of Systematic Defects (Abstract)

pp. 349-354

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Delay Fault Diagnosis in Sequential Circuits (Abstract)

Serge Pravossoudovitch

Arnaud Virazel

Olivia Riewer

pp. 355-360

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A Partially-Exhaustive Gate Transition Fault Model (Abstract)

pp. 361-364

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An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing (Abstract)

pp. 367-372

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LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits (Abstract)

pp. 373-378

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A Jitter Characterizing BIST with Pulse-Amplifying Technique (Abstract)

An-Sheng Chao

Soon-Jyh Chang

pp. 379-384

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A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method (Abstract)

pp. 385-388

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New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults (Abstract)

pp. 391-396

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Testability Exploration of 3-D RAMs and CAMs (Abstract)

Yu-Jen Huang

Jin-Fu Li

pp. 397-402

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Fault Diagnosis Using Test Primitives in Random Access Memories (Abstract)

Zaid Al-Ars

Said Hamdioui

pp. 403-408

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Test Generation for Designs with On-Chip Clock Generators (Abstract)

Xijiang Lin

Mark Kassab

pp. 411-417

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On the Generation of Functional Test Programs for the Cache Replacement Logic (Abstract)

pp. 418-423

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Compact Test Generation for Small-Delay Defects Using Testable-Path Information (Abstract)

Dong Xiang

Boxue Yin

Krishendu Chakrabarty

pp. 424-429

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At-Speed Scan Test Method for the Timing Optimization and Calibration (Abstract)

pp. 430-433

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M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay (Abstract)

pp. 437-442

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Analysis of Resistive Bridging Defects in a Synchronizer (Abstract)

pp. 443-449

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On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification (Abstract)

pp. 450-455

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Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks (Abstract)

pp. 456-461

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Author Index (PDF)

pp. 462-465

Roster Page (PDF)

pp. 466