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2009 Asian Test Symposium
Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test
Taichung, Taiwan
November 23-November 26
ISBN: 978-0-7695-3864-8
| ASCII Text | x | ||
| Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li, "Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test," 2012 IEEE 21st Asian Test Symposium, pp. 163-168, 2009 Asian Test Symposium, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/ATS.2009.72, author = {Chen-I Chung and Jyun-Sian Jhou and Ching-Hwa Cheng and Sih-Yan Li}, title = {Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test}, journal ={2012 IEEE 21st Asian Test Symposium}, volume = {0}, year = {2009}, issn = {1081-7735}, pages = {163-168}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2009.72}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 21st Asian Test Symposium TI - Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test SN - 1081-7735 SP163 EP168 A1 - Chen-I Chung, A1 - Jyun-Sian Jhou, A1 - Ching-Hwa Cheng, A1 - Sih-Yan Li, PY - 2009 VL - 0 JA - 2012 IEEE 21st Asian Test Symposium ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2009.72
The self wide-range (26%~76%), fine-scale (34ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.
Citation:
Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li, "Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test," ats, pp.163-168, 2009 Asian Test Symposium, 2009
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