To cope with increasing in-field failure rates for cost-sensitive electronic products, a low-overhead online checking methodology -- Time-Multiplexed Online Checking (TMOC) -- was proposed and demonstrated in [1]. In this paper, we study the area overhead required for employing TMOC in an embedded Field Programmable Gate Array (eFPGA) core. The overheads caused by the relatively low logic density of eFPGA and the interface routing between a design module and its TMOC checker are examined in detail. In a case study of an H.264 decoder design [2], TMOC is compared to a dedicated duplication-based online checking scheme [3], which typically incurs more than 100% area overhead. Experimental results show that TMOC provides significant chip area overhead reduction for online checkers. A reduction of 68% is achieved when one checker is shared by 62 design partitions, for example. TMOC can also help reduce dynamic power overhead of online checking by increasing the number of partitions, at the cost of increased fault detection latency in some partitions.