Nov. 20, 2006 to Nov. 23, 2006
Chia Yee Ooi , Nara Institute of Science and Technology Kansai Science City
Hideo Fujiwara , Nara Institute of Science and Technology Kansai Science City
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2006.11
VLSI design has moved from bottom-up design approach to top-down design methodology with the aid of advanced Computer-Aided Design (CAD) technology. This paper introduces a new scan design technique as a design-for-test (DFT) method for sequential circuits by exploiting the information of thru functions available at high-level description of the circuit. This DFT method reduces the number of flip-flops to be converted into scan flip-flops because some existing thru functions allow the flip-flops to be controllable from primary inputs or observable at primary outputs or both. Moreover, the DFT method can be applied to both structural RT-level circuits and gate-level circuits. The paper also presents a test generation procedure for the augmented sequential circuits using a combinational ATPG tool. The experimental results show the comparison of our DFT method with conventional scan techniques in terms of hardware overhead, test generation time, fault coverage, fault efficiency and test application time.
Chia Yee Ooi, Hideo Fujiwara, "A New Scan Design Technique Based on Pre-Synthesis Thru Functions", ATS, 2006, 2012 IEEE 21st Asian Test Symposium, 2012 IEEE 21st Asian Test Symposium 2006, pp. 163-168, doi:10.1109/ATS.2006.11