13th Asian Test Symposium (ATS'04) Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects Kenting, Taiwan November 15-November 17 ISBN: 0-7695-2235-1
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.58
This paper presents comprehensive analytic models that consider both the case of a weak bridge, and the combination of a weak bridge and crosstalk between two interconnects. Our models capture the induced signal delay and pulse as a function of the parameters of the circuit and input signals. Our results are compared with HSPICE and shown to be accurate. A simulator is developed that implements our models and accurately captures timing (delay) characteristics of a circuit. We contrast our results with others, and show the benefits of this new model as well as the ability to predict the range of resistance that leads to delay errors.
Citation:
Lei Wang, Sandeep K. Gupta, Melvin A. Breuer, "Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects," ats, pp.440-447, 13th Asian Test Symposium (ATS'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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