CSDL - Proceedings A

Message from the Program Chairs (PDF)

pp. xvi

ATS Steering Committee (PDF)

pp. xvii

The 12th Asian Test Symposium Committee (PDF)

pp. xviii

Program Committee (PDF)

pp. xix

Reviewers (PDF)

pp. xxi

Call for Papers ATS 2004 (PDF)

pp. 514

TTTC Activities Board (PDF)

pp. 515

Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits (PDF)

Plenary Session: Keynote Address

Kewal K. Saluja, University of Wisconsin - Madison

pp. 2

Leveraging Infrastructure IP for SoC Yield (PDF)

Yervant Zorian, Virage Logic Corp

pp. 3

Session 1A: Design for Testability

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Reducing Scan Shifts Using Folding Scan Trees (Abstract)

Hiroyuki Yotsuyanagi, University of Tokushima

Toshimasa Kuchii, Sharp Corporation

Shigeki Nishikawa, Sharp Corporation

Masaki Hashizume, University of Tokushima

Kozo Kinoshita, Osaka Gakuin University

pp. 6

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Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning (Abstract)

Dong Xiang, Tsinghua University

Ming-Jing Chen, Tsinghua University

Jia-Guang Sun, Tsinghua University

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 12

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IC Reliability Simulator ARET and Its Application in Design-for-Reliability (Abstract)

Xiangdong Xuan, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

Adit D. Singh, Auburn University

Namsoo P. Kim, The Boeing Company

Mark T. Chisa, The Boeing Company

pp. 18

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Session 1B: Memory Testing 1

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Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces (Abstract)

Zaid Al-Ars, Delft University of Technology

Ad J. van de Goor, Delft University of Technology

pp. 24

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Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells (Abstract)

Yuki Yamagata, Tokyo Metropolitan University

Kenichi Ichino, Tokyo Metropolitan University

Masayuki Arai, Tokyo Metropolitan University

Satoshi Fukumoto, Tokyo Metropolitan University

Kazuhiko Iwasaki, Tokyo Metropolitan University

Masayuki Sato, INNOTECH Corp.

Hiroyuki Itabashi, INNOTECH Corp.

Takashi Murai, INNOTECH Corp.

Nobuyuki Otsuka, INNOTECH Corp.

pp. 28

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Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool (Abstract)

F. Bertuccelli, Aurelia Microelettronica S.p.A

F. Bigongiari, Aurelia Microelettronica S.p.A

A. S. Brogna, Universit? di Pisa

G. Di Natale, Politecnico di Torino

P. Prinetto, Politecnico di Torino

R. Saletti, Universit? di Pisa

pp. 32

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Session 1C: Fault Diagnosis 1

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Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults (Abstract)

Yu-Chiun Lin, National Tsing-Hua University

Shi-Yu Huang, National Tsing-Hua University

pp. 38

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Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults (Abstract)

Yu Huang, Mentor Graphics Corporation

Wu-Tung Cheng, Mentor Graphics Corporation

Cheng-Ju Hsieh, Faraday Technology Corporation

Huan-Yung Tseng, Faraday Technology Corporation

Alou Huang, Faraday Technology Corporation

Yu-Ting Hung, Faraday Technology Corporation

pp. 44

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A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM* Comparison Model (Abstract)

Xiaofan Yang, Chongqing University

pp. 50

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Session 2A: Delay Testing

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Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models (Abstract)

Tsuyoshi Iwagaki, Nara Institute of Science and Technology

Satoshi Ohtake, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 58

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On Estimation of Fault Efficiency for Path Delay Faults (Abstract)

Masayasu Fukunaga, Kyushu Institute of Technology

Seiji Kajihara, Kyushu Institute of Technology

Sadami Takeoka, Matsushita Electric Industrial Co., Ltd. Semiconductor Company

pp. 64

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Software-Based Delay Fault Testing of Processor Cores (Abstract)

Virendra Singh, Nara Institute of Science and Technology and Central Electronics Engineering Research Institute

Michiko Inoue, Nara Institute of Science and Technology

Kewal K Saluja, University of Wisconsin-Madison

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 68

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A DFT Approach for Path Delay Faults in Interconnected Circuits (Abstract)

Irith Pomeranz, Purdue University

Sudhakar M. Reddy, University of Iowa

pp. 72

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Session 2B: BIST

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Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity (Abstract)

Sukanta Das, Bengal Engineering College

Anirban Kundu, Bengal Engineering College

Subhayan Sen, Bengal Engineering College

Biplab K. Sikdar, Bengal Engineering College

P. Pal Chaudhuri, Bengal Engineering College

pp. 78

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A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations (Abstract)

Ehsan Atoofian, University of Tehran

Zainalabedin Navabi, University of Tehran

pp. 84

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A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic (Abstract)

Md. Rafiqul Islam, University of Dhaka

Hafiz Md Hasan Babu, University of Dhaka

Mohammad Abdur Rahim Mustafa, University of Dhaka

Md. Sumon Shahriar, University of Dhaka

pp. 90

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Session 2C: Software Testing 1

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Domain Testing Based on Character String Predicate (Abstract)

Ruilian Zhao, Beijing University of Chemical Technology

Michael R. Lyu, Chinese University of Hong Kong

Yinghua Min, Chinese Academy of Sciences in Beijing

pp. 96

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Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov Chains (Abstract)

Matthias Beyer, University of Erlangen-Nuremberg

Winfried Dulz, University of Erlangen-Nuremberg

Fenhua Zhen, University of Erlangen-Nuremberg

pp. 102

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Efficiency Analysis and Safety Assessment of Automatic Testing for Safety-Critical Software (Abstract)

Fangmei Wu, Tongji University

Lei Huang, Tongji University

pp. 106

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An Expression?s Single Fault Model and the Testing Methods (Abstract)

Yunzhan Gong, Academy of Armored Forces Engineering Beijing

Wanli Xu, Academy of Armored Forces Engineering Beijing

Xiaowei Li, Chinese Academy of Science

pp. 110

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Session 3A: Mixed-Signal Testing

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PLL Based High Speed Functional Testing (Abstract)

Jayasanker Jayabalan, National University of Singapore

Chee Kiang Goh, Infineon Technologies

Ooi Ban Leong, National University of Singapore

Leong Mook Seng, National University of Singapore

Mahadevan K. Iyer, Institute of Microelectronics

Andrew A.O. Tay, National University of Singapore

pp. 116

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Mike W. T. Wong, Hong Kong Polytechnic University

pp. 120

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A Sigma-Delta Modulation Based BIST Scheme for A/D Converters (Abstract)

Kuen-Jong Lee, National Cheng Kung University

Soon-Jyh Chang, National Cheng Kung University

Ruei-Shiuan Tzeng, National Cheng Kung University

pp. 124

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Session 3B: Test Compaction 1

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A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint (Abstract)

Toshinori Hosokawa, STARC

Hiroshi Date, STARC

Masahide Miyazaki, STARC

Michiaki Muraoka, STARC

Hideo Fujiwara, Nara Institute Science and Technology

pp. 130

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Optimal Scan Tree Construction with Test Vector Modification for Test Compression (Abstract)

Kohei Miyase, Kyusyu Institute of Technology

Seiji Kajihara, Kyusyu Institute of Technology and Kyushu Institute of Technology

pp. 136

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STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data (Abstract)

Bernd Koenemann, Cadence Design Systems, Inc.

pp. 142

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Session 3C: RTL Verification

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Automatic Design Validation Framework for HDL Descriptions via RTL ATPG (PDF)

Liang Zhang, Virginia Tech

Michael Hsiao, Virginia Tech

Indradeep Ghosh, Fujitsu Laboratories of America Inc.

pp. 148

An Automatic Circuit Extractor for RTL Verification (Abstract)

Tun Li, National University of Defense Technology

Yang Guo, National University of Defense Technology

Sikun Li, National University of Defense Technology

pp. 154

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An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains (Abstract)

Tao Lv, Chinese Academy of Sciences

Jianping Fan, Chinese Academy of Sciences

Xiaowei Li, Chinese Academy of Sciences

pp. 161

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Session 4A: Enhanced Delay Testing and ATPG

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Delay Testing of MOS Transistor with Gate Oxide Short (Abstract)

M. Renovell, Universit? de Montpellier II

J.M. Galli?re, Universit? de Montpellier II

F. Aza?, Universit? de Montpellier II

Y. Bertrand, Universit? de Montpellier II

pp. 168

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An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults (Abstract)

Arani Sinha, University of Southern California

Sandeep K. Gupta, University of Southern California

Melvin A. Breuer, University of Southern California

pp. 174

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Delay Test Pattern Generation Considering Crosstalk-Induced Effects (Abstract)

Huawei Li, Chinese Academy of Sciences

Yue Zhang, Academy of Armored Forces Engineering

Xiaowei Li, Chinese Academy of Sciences

pp. 178

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Automated Test Model Generation from Switch Level Custom Circuits (Abstract)

Magdy S. Abadir, Motorola, Inc.

Jing Zeng, Motorola, Inc.

Carol Pyron, Motorola, Inc.

Juhong Zhu, Sun Microsystem

pp. 184

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Session 4B: Test Power

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Power Conscious BIST Design for Sequential Circuits Using ghost-FSM (Abstract)

S Roy, Kalyani Govt. Engineering College

Biplab K Sikdar, Bengal Engineering College

pp. 190

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Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits (Abstract)

Yongjun Xu, Chinese Academy of Sciences

Zuying Luo, Tsinghua University

Zhiguo Chen, Chinese Academy of Sciences and University of Electronic Science and Technology of China

Xiaowei Li, Chinese Academy of Sciences

pp. 196

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Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test (Abstract)

Ozgur Sinanoglu, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 202

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Session 4C: Software Testing 2

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Analysis of Software Test Item Generation — Comparison between High Skilled and Low Skilled Engineers (Abstract)

Masayuki Hirayama, TOSHIBA Corporation

Tetsuya Yamamoto, TOSHIBA Corporation

Osamu Mizuno, Osaka University

Tohru Kikuno, Osaka University

pp. 210

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Conformance Test of Distributed Transaction Service (Abstract)

Chang Xu, Chinese Academy of Sciences

Beihong Jin, Chinese Academy of Sciences

pp. 216

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Build-In-Self-Test for Software (Abstract)

Shiyi Xu, Shanghai University

pp. 220

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Testing the Conformity of Transactional Attributes of Components by Simulation (Abstract)

Hui-Qun Zhao, China University Technology

Qin-Xin Gao, Northeastern University

Yuan Gao, Northeastern University

pp. 224

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Session 5A: Fault Diagnosis 2

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Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information (Abstract)

Baris Arslan, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 230

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Fault Diagnosis for Physical Defects of Unknown Behaviors (Abstract)

Xiaoqing Wen, SynTest Technologies, Inc.

Hideo Tamamoto, Akita University

Kewal K. Saluja, University of Wisconsin-Madison

Kozo Kinoshita, Osaka Gakuin University

pp. 236

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Fault Detection for Testable Realizations of Multiple-Valued Logic Functions (Abstract)

Pan Zhongliang, South China Normal University

pp. 242

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Session 5B: Memory Testing 2

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Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders (Abstract)

Luigi Dilillo, Universit? de Montpellier II / CNRS

Patrick Girard, Universit? de Montpellier II / CNRS

Serge Pravossoudovitch, Universit? de Montpellier II / CNRS

Arnaud Virazel, Universit? de Montpellier II / CNRS

Simone Borri, Infineon Technologies France

pp. 250

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Defect Oriented Fault Analysis for SRAM (Abstract)

Rei-Fu Huang, National Tsing Hua University

Yung-Fa Chou, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 256

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A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs (Abstract)

L. Kalyan Kumar, Indian Institute of Technology-Madras

Amol J. Mupid, Indian Institute of Technology-Madras

Aditya S. Ramani, Indian Institute of Technology-Madras

V. Kamakoti, Indian Institute of Technology-Madras

pp. 262

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Session 5C: SOC Test

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Between-Core Vector Overlapping for Test Cost Reduction in Core Testing (Abstract)

Tsuyoshi Shinogi, Mie University

Yuki Yamada, Mie University

Terumine Hayashi, Mie University

Tomohiro Yoshikawa, Mie University

Shinji Tsuruoka, Mie University

pp. 268

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The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology (Abstract)

Pedram A. Riahi, Northeastern University

Zainalabedin Navabi, Northeastern University

Fabrizio Lombardi, Northeastern University

pp. 274

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A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores (Abstract)

Zhigang Jiang, University of Southern California

Sandeep K. Gupta, University of Southern California

pp. 278

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Session 6A: DFT Synthesis

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Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability (Abstract)

Hafizur Rahaman, WB University of Technology

Debesh K. Das, Jadavpur University

Bhargab B. Bhattacharya, Indian Statistical Institute

pp. 284

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BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability (Abstract)

Junhao Shi, University of Bremen

Goerschwin Fey, University of Bremen

Rolf Drechsler, University of Bremen

pp. 290

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Test Synthesis for Datapaths Using Datapath-Controller Functions (Abstract)

Michiko Inoue, Nara Institute of Science and Technology

Kazuhiro Suzuki, Nara Institute of Science and Technology

Hiroyuki Okamoto, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 294

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Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis (Abstract)

Dong Xiang, Tsinghua University

Shan Gu, Tsinghua University

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 300

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Session 6B: Test Scheduling

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Optimal System-on-Chip Test Scheduling (Abstract)

Erik Larsson, Link?pings Universitet and Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 306

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SOC Test Time Minimization Under Multiple Constraints (Abstract)

Julien Pouget, Link?pings Universitet

Erik Larsson, Link?pings Universitet

Zebo Peng, Link?pings Universitet

pp. 312

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Test Time Minimization for Hybrid BIST of Core-Based Systems (Abstract)

Gert Jervan, Link?ping University

Petru Eles, Link?ping University

Zebo Peng, Link?ping University

Raimund Ubar, Tallinn Technical University

Maksim Jenihhin, Tallinn Technical University

pp. 318

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Session 6C: Measurement

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On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization (Abstract)

Tian Xia, University of Vermont

Jien-Chung Lo, University of Rhode Island

pp. 326

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An On-Chip Jitter Measurement Circuit for the PLL (Abstract)

Chin-Cheng Tsai, National Chaio Tung University

Chung-Len Lee, National Chaio Tung University

pp. 332

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A Low-Cost Jitter Measurement Technique for BIST Applications (Abstract)

Jui-Jer Huang, National Taiwan University

Jiun-Lang Huang, National Taiwan University

pp. 336

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Measurement-Based Modeling with Adaptive Sampling (Abstract)

Junfeng Wang, University of Electric Science and Technology of China

Jianhua Yang, Chinese Academy of Sciences

Gaogang Xie, Chinese Academy of Sciences

Mingtian Zhou, University of Electric Science and Technology of China

Zhongcheng Li, Chinese Academy of Sciences

pp. 340

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Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing (Abstract)

Session 7A: Test Economics

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Baosheng Wang, University of British Columbia

Yong B. Cho, Konkuk University

Sassan Tabatabaei, Vector 12 Corporation

Andr? Ivanov, University of British Columbia

pp. 348

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Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method (Abstract)

Yuxin Tian, Texas A&M University

Michael R. Grimaila, Texas A&M University

Weiping Shi, Texas A&M University

M. Ray Mercer, Texas A&M University

pp. 354

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Lowering Cost of Test: Parallel Test or Low-Cost ATE? (Abstract)

Jochen Rivoir, Agilent Technologies

pp. 360

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Session 7B: Memory Testing 3

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A Processor-Based Built-In Self-Repair Design for Embedded Memories (Abstract)

Chin-Lung Su, National Tsing Hua University

Rei-Fu Huang, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 366

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March SL: A Test For All Static Linked Memory Faults (Abstract)

Said Hamdioui, Delft University of Technology and Intel Corporation

Zaid Al-Ars, Delft University of Technology

Ad J. van de Goor, Delft University of Technology

Mike Rodgers, Intel Corporation

pp. 372

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Testing Delay Faults in Embedded CAMs (Abstract)

Xiaogang Du, University of Iowa

Sudhakar M. Reddy, University of Iowa

Joseph Rayhawk, Mentor Graphics Corporation

Wu-Tung Cheng, Mentor Graphics Corporation

pp. 378

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Stress Test for Disturb Faults in Non-Volatile Memories (Abstract)

Mohammad Gh. Mohammad, Kuwait University

Kewal K. Saluja, University of Wisconsin-Madison

pp. 384

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Session 7C: Current Test

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A BIST Circuit for I_DDQ Tests (Abstract)

Masaki Hashizume, University of Tokushima

Teppei Takeda, University of Tokushima

Hiroyuki Yotsuyanagi, University of Tokushima

Takeomi Tamesada, University of Tokushima

Yukiya Miura, Tokyo Metropolitan University

Kozo Kinoshita, Osaka Gakuin University

pp. 390

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At-Speed Current Testing (Abstract)

Yinghua Min, Hunan University

Jishun Kuang, Hunan University

Xiaoyan Niu, Hunan University

pp. 396

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I_DDT ATPG Based on Ambiguous Delay Assignments (Abstract)

Jishun Kuang, Hunan University

Yu Wang, Hunan University

Xiaofen Wei, Hunan University

Changnian Zhang, University of Regina

pp. 400

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Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test (Abstract)

Hiroyuki Michinishi, Okayama University of Science

Tokumi Yokohira, Okayama University

Takuji Okamoto, Okayama University of Science

Toshifumi Kobayashi, Mitsubishi Electric Co.

Tsutomu Hondo, Sharp Takaya Electronics Industry Co.,Ltd.

pp. 406

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Session 8A: SOC DFT

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A DFT Selection Method for Reducing Test Application Time of System-on-Chips (Abstract)

Masahide Miyazaki, Semiconductor Technology Academic Research Center

Toshinori Hosokawa, Semiconductor Technology Academic Research Center

Hiroshi Date, Semiconductor Technology Academic Research Center

Michiaki Muraoka, Semiconductor Technology Academic Research Center

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 412

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Sharing BIST with Multiple Cores for System-on-a-Chip (Abstract)

Huaguo Liang, Hefei University of Technology

Cuiyun Jiang, Hefei University of Technology

pp. 418

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Designing Multiple Scan Chains for Systems-on-Chip (Abstract)

Md. Saffat Quasem, University of Southern California

Sandeep Gupta, University of Southern California

pp. 424

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Optimizing Test Access Mechanism under Constraints by Genetic Local Search Algorithm (Abstract)

Yingxiang Wang, Fudan University

Weikang Huang, Fudan University

pp. 428

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Session 8B: Test Compaction 2

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Test Data Volume Reduction by Test Data Realignment (Abstract)

Irith Pomeranz, Purdue University

Sudhakar M. Reddy, University of Iowa

pp. 434

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Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction (Abstract)

Yinhe Han, Chinese Academy of Science

Yongjun Xu, Chinese Academy of Science

Huawei Li, Chinese Academy of Science

Xiaowei Li, Chinese Academy of Science

Anshuman Chandra, Synopsys, Inc.

pp. 440

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Test Response Compression Based on Huffman Coding (Abstract)

Hideyuki Ichihara, Hiroshima City University

Michihiro Shintani, Hiroshima City University

Toshihiro Ohara, Hiroshima City University

Tomoo Inoue, Hiroshima City University

pp. 446

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Session 8C: Functional Testing/Reliability

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Probability Model for Faults in Large-Scale Multicomputer Systems (Abstract)

Gaocai Wang, Central South University

Jianer Chen, Central South University

Guojun Wang, Central South University

Songqiao Chen, Central South University

pp. 452

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Design Retargetable Platform System for Microprocessor Functional Test (Abstract)

Ling Liu, Peking University

Wennan Feng, Peking University

Song Jia, Peking University

Anping Jiang, Peking University

Lijiu Ji, Peking University

pp. 458

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Assessing Software Implemented Fault Detection and Fault Tolerance Mechanisms (Abstract)

P. Gawkowski, Warsaw University of Technology

J. Sosnowski, Warsaw University of Technology

pp. 462

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Briefing a New Approach to Improve the EMI Immunity of DSP Systems (Abstract)

Fabian Vargas, Catholic University - PUCRS

Rubem D. R. Fagundes, Catholic University - PUCRS

Daniel Barros Jr., Catholic University - PUCRS

Diogo B. Brum, Catholic University - PUCRS

pp. 468

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Session 9A: Formal Verification

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Design Error Diagnosis Based on Verification Techniques (Abstract)

Guanghui Li, Chinese Academy of Sciences and Zhejiang Forestry College

Ming Shao, Chinese Academy of Sciences

Xiaowei Li, Chinese Academy of Sciences

pp. 474

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SAT-Based Algorithm of Verification for Port Order Fault (Abstract)

Ming Shao, Chinese Academy of Sciences

Guanghui Li, Chinese Academy of Sciences

Xiaowei Li, Chinese Academy of Sciences

pp. 478

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Equivalence Checking Using Independent Cuts (Abstract)

Zhan Xu, Zhejiang University

Xiaolang Yan, Zhejiang University

Yongjiang Lu, Zhejiang University

Haitong Ge, Zhejiang University

pp. 482

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Session 9B: Software Testing 3

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A Method to Calculate the Reliability of Component-Based Software (Abstract)

Yuan Zhu, Shanghai Normal University

Jianhua Gao, Shanghai Normal University

pp. 488

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An Object-Oriented Program Automatic Execute Model and the Research of Algorithm (Abstract)

Da-Hai Jin, Armored Force Engineering Institute

Yun-Zhan Gong, Armored Force Engineering Institute

pp. 492

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User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NT (Abstract)

Jin-Min Yang, Hunan University

Da-Fang Zhang, Hunan University

Xue-Dong Yang, University of Regina

pp. 496

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Poster Session

RTL Concurrent Fault Simulation (PDF)

Li Shen, Chinese Academy of Sciences

pp. 502

Property Classification for Functional Verification Based (PDF)

Ming Zhu, Tsinghua University

Jinian Bian, Tsinghua University

Weimin Wu, Tsinghua University

Hongxi Xue, Tsinghua University

pp. 503

Error Detection and Correction in VLSI Systems by Online Testing and Retrying (PDF)

Jian-Hui Jiang, Tongji University

pp. 504

Testability Improvement During High-Level Synthesis (PDF)

Saeed Safari, Sharif University of Technology

Hadi Esmaeilzadeh, University of Tehran

Amir-Hossein Jahangir, Sharif University of Technology

pp. 505

A Test Architecture for System-on-a-Chip (PDF)

Yong-sheng Wang, Harbin Institute of Technology

Li-yi Xiao, Harbin Institute of Technology

Ming-yan Yu, Harbin Institute of Technology

Jin-xiang Wang, Harbin Institute of Technology

Yi-zheng Ye, Harbin Institute of Technology

pp. 506

Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST (PDF)

He Hu, Tsinghua University

Sun Yihe, Tsinghua University

pp. 507

Test Pattern Length Required to Reach the Desired Fault Coverage (PDF)

Junichi Hirase, Matsushita Electric Industrial Co., Ltd.

pp. 508

Damage Size and Software Safety Demonstration Stress Testing (PDF)

Zhongwei Xu, Tongji University

Bangxing Chen, Tongji University

pp. 509

Study on the Cost/Benefit/Optimization of Software Safety Test (PDF)

Meng Li, Tongji University

Zhu Xu, Tongji University

pp. 510

Author Index

Author Index (PDF)

pp. 511