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11th Asian Test Symposium (ATS'02)
On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications
Guam, USA
November 18-November 20
ISBN: 0-7695-1825-7
| ASCII Text | x | ||
| Octavian Petre, Hans G. Kerkhoff, "On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications," 2012 IEEE 21st Asian Test Symposium, pp. 122, 11th Asian Test Symposium (ATS'02), 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/ATS.2002.1181698, author = {Octavian Petre and Hans G. Kerkhoff}, title = {On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications}, journal ={2012 IEEE 21st Asian Test Symposium}, volume = {0}, year = {2002}, issn = {1081-7735}, pages = {122}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181698}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 21st Asian Test Symposium TI - On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications SN - 1081-7735 SP EP A1 - Octavian Petre, A1 - Hans G. Kerkhoff, PY - 2002 KW - null VL - 0 JA - 2012 IEEE 21st Asian Test Symposium ER - | |||
During the last few years, new synchronization techniques to send data between IC?s at increasingly high datarates have been developed. Some of them rely on digital delay lines. The timing accuracy of the delay lines is crucial for a good functionality of the synchronization mechanism. This paper will present a strategy to measure the tap-delays of a digital delay-line, using the well-known oscillation technique. The occurring measurement error for the presented technique has been calculated. Towards the end of the paper, a new delay-line scheme is shown. The tap-delay measurement becomes much more accurate for this delay-line than for a standard delay-line.
Citation:
Octavian Petre, Hans G. Kerkhoff, "On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications," ats, pp.122, 11th Asian Test Symposium (ATS'02), 2002
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