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10th Asian Test Symposium (ATS'01)
Kyoto, Japan
November 19-November 21
ISBN: 0-7695-1378-6
Table of Contents
Reviewers (PDF)
pp. xxiii
Plenary Session: Keynote Address
Session 1A: Design for Testability - Chair: Ermenfried Prochaska, Fachhochschule Heilbronn, Germany
Md. Altaf-Ul-Amin, Nara Institute of Science and Technology
Satoshi Ohtake, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 11
Session 1B: Fault Modeling for Memories - Chair: Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan
Said Hamdioui, Intel Corporation and Delft University of Technology
Ad J. van de Goor, Delft University of Technology
David Eastwick, Intel Corporation
Mike Rodgers, Intel Corporation
pp. 37
Zaid Al-Ars, Delft University of Technology
Ad J. van de Goor, Delft University of Technology
Jens Braun, Infineon Technologies AG
Detlev Richter, Infineon Technologies AG
pp. 43
Session 1C: Diagnosis Session - Chair: Shiyi Xu, Shanghai University, China
Hiroshi Takahashi, Ehime University
Marong Phadoongsidhi, University of Wisconsin -Madison
Yoshinobu Higami, Ehime University
Kewal K. Saluja, University of Wisconsin -Madison
Yuzo Takamatsu, Ehime University
pp. 63
Session 2A: ATPG - Chair: Christian Landrault, LIRMM, France
Session 2B: Embedded Memory Test - Chair: Yervant Zorian, Logic Vision, Inc., USA
Kuo-Liang Cheng, National Tsing Hua University
Chia-Ming Hsueh, National Tsing Hua University
Jing-Reng Huang, National Tsing Hua University
Jen-Chieh Yeh, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 91
D. Appello, STMicroelectronics
F. Corno, Politecnico di Torino
M. Giovinetto, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
pp. 97
Chih-Wea Wang, National Tsing Hua University
Ruey-Shing Tzeng, National Tsing Hua University
Chi-Feng Wu, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
Shi-Yu Huang, National Tsing Hua University
Shyh-Horng Lin, SynTest Technologies,Inc.
Hsin-Po Wang, SynTest Technologies,Inc.
pp. 103
Session 2C: IDDQ and Diagnosis Test - Chair: Hiroshi Yokoyama, Akita University, Japan
Teppei Takeda, The University of Tokushima
Masaki Hashizume, The University of Tokushima
Masahiro Ichimiya, The University of Tokushima
Hiroyuki Yotsuyanagi, The University of Tokushima
Yukiya Miura, Tokyo Metropolitan University
Kozo Kinoshita, Osaka Gakuin University
pp. 111
Session 3A: Test Compaction - Chair: Toshinori Hosokawa, Semiconductor Technology Academic Research Center, Japan
Hideyuki Ichihara, Hiroshima City University
Atsuhiro Ogawa, Hiroshima City University
Tomoo Inoue, Hiroshima City University
Akio Tamura, Hiroshima City University
pp. 143
Session 3B: Pattern Generation for Memory Test - Chair: Tetsuo Tada, Mitsubishi Electric Corporation, Japan
Mill-Jer Wang, Vanguard International Semiconductor Corporation
R.-L. Jiang, Vanguard International Semiconductor Corporation
J.-W. Hsia, Vanguard International Semiconductor Corporation
Chih-Hu Wang, Chung-Hua University
Jwu E. Chen, Chung-Hua University
pp. 151
Alfredo Benso, Politecnico di Torino
Stefano Di Carlo, Politecnico di Torino
Giorgio Di Natale, Politecnico di Torino
Paolo Prinetto, Politecnico di Torino
pp. 157
S. Demidenko, Massey University
A. van de Goor, Delft University of Technology
S. Henderson, Massey University
P. Knoppers, Delft University of Technology
pp. 164
Session 3C: Virtual Tester and Beam Testing - Chair: Koji Nakamae, Osaka University, Japan
Norio Kuji, NTT Electronics Co. and NTT Telecommunications Energy Laboratories
Takako Ishihara, NTT Electronics Co. and NTT Telecommunications Energy Laboratories
pp. 179
Session 4A: SoC Test Access Mechanism - Chair: Hiroshi Date, ABEL Systems Inc., Japan
Session 4B: RTL ATPG - Chair: Jacob A. Abraham, University of Texas at Austin, USA
Huawei Li, Chinese Academy of Sciences
Yinghua Min, Chinese Academy of Sciences
Zhongcheng Li, Chinese Academy of Sciences
pp. 213
Zhigang Yin, Chinese Academy of Sciences
Yinghua Min, Chinese Academy of Sciences
Xiaowei Li, Chinese Academy of Sciences
pp. 219
Fulvio Corno, Politecnico di Torino
Gianluca Cumani, Politecnico di Torino
Matteo Sonza Reorda, Politecnico di Torino
Giovanni Squillero, Politecnico di Torino
pp. 225
Session 4C: Delay Test - Chair: Jacob Savir, New Jersey Institute of Technology, USA
Yun Shao, University of Iowa
Sudhakar M. Reddy, University of Iowa
Seiji Kajihara, Kyushu Institute of Technology
Irith Pomeranz, Purdue University
pp. 233
Session 5A: SoC Test Scheduling - Chair: Prab Varma, Veritable Inc., USA
Y. Bonhomme, Universit? Montpellier II /CNRS
P. Girard, Universit? Montpellier II /CNRS
L. Guiller, Universit? Montpellier II /CNRS
C. Landrault, Universit? Montpellier II /CNRS
S. Pravossoudovitch, Universit? Montpellier II /CNRS
pp. 253
Yu Huang, University of Iowa
Wu-Tung Cheng, Mentor Graphics Corporation
Chien-Chung Tsai, Mentor Graphics Corporation
Nilanjan Mukherjee, Mentor Graphics Corporation
Omer Samman, Mentor Graphics Corporation
Yahya Zaidan, Mentor Graphics Corporation
Sudhakar M. Reddy, University of Iowa
pp. 265
Session 5B: FSM Test - Chair: Hiroshi Takahashi, Ehime University, Japan
P. K. Lala, University of Arkansas
A. Walker, North Carolina A&T State University
pp. 273
Samrat Goswami, Indian Institute of Technology at Kharagpur
Anupam Chanda, Indian Institute of Technology at Kharagpur
D. Roy Choudhury, Indian Institute of Technology at Kharagpur
pp. 279
Biplab K Sikdar, Bengal Engineering College
Samir Roy, Kalyani Government Engineering College
Debesh K Das, Jadavpur University
pp. 285
Session 5C: Online Testing and Fault Injection line - Chair: Masahiro Tsunoyama, Niigata Institute of Technology, Japan
Alfredo Benso, Politecnico di Torino
Stefano Di Carlo, Politecnico di Torino
Giorgio Di Natale, Politecnico di Torino
Paolo Prinetto, Politecnico di Torino
Luca Tagliaferri, Politecnico di Torino
pp. 299
P. Civera, Politecnico di Torino
L. Macchiarulo, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
pp. 304
Session 6A: Advances in BIST - Chair: Kazuhiko Iijima, Logic Vision, Inc., Japan
Ken-ichi Yamaguchi, Nara Institute of Science and Technology
Hiroki Wada, Nara Institute of Science and Technology
Toshimitsu Masuzawa, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 313
Sobeeh Almukhaizim, University of California at San Diego
Peter Petrov, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 319
Bernd Koenemann, IBM Microelectronics
Carl Barnhart, IBM Microelectronics
Brion Keller, IBM Microelectronics
Tom Snethen, IBM Microelectronics
Owen Farnsworth, IBM Microelectronics
Donald Wheater, IBM Microelectronics
pp. 325
Session 6B: Analog Test - Chair: Yasuo Furukawa, Advantest Corporation, Japan
Zhen Guo, New Jersey Institute of Technology
Xi Min Zhang, New Jersey Institute of Technology
Jacob Savir, New Jersey Institute of Technology
Yun-Qing Shi, New Jersey Institute of Technology
pp. 338
Session 6C: Fault Tolerance - Chair: Hideo Ito, Chiba University, Japan
Naotake Kamiura, Himeji Institute of Technology
Yasuyuki Taniguchi, Sharp Corporation
Teijiro Isokawa, Himeji Institute of Technology
Nobuyuki Matsui, Himeji Institute of Technology
pp. 359
Session 7A: Various Ideas for BIST - Chair: Tokumi Yokohira, Okayama University, Japan
Ismet Bayraktaroglu, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 373
Kenichi Ichino, Tokyo Metropolitan University
Takeshi Asakawa, Tokyo Metropolitan University
Satoshi Fukumoto, Tokyo Metropolitan University
Kazuhiko Iwasaki, Tokyo Metropolitan University
Seiji Kajihara, Kyushu Institute of Technology
pp. 379
Biplab K Sikdar, Bengal Engineering College
Niloy Ganguly, IISWBM
Aniket Karmakar, Bengal Engineering College
Subha Sankar Chowdhury, Bengal Engineering College
P. Pal Chaudhuri, Bengal Engineering College
pp. 385
Session 7B: Analog/Mixed Signal Test - Chair: Michel Renovell, LIRMM, France
Jeng-Horng Tsai, National Tsing Hua University
Ming-Jun Hsiao, National Tsing Hua University
Tsin-Yuan Chang, National Tsing Hua University
pp. 423
Session 7C: Verification - Chair: Kiyoharu Hamaguchi, Osaka University, Japan
Poster Session 1: DFT Application to Real Chips
Y. Sato, Hitachi, Ltd.
M. Sato, Hitachi, Ltd.
K. Tsutsumida, Hitachi, Ltd.
T. Ikeya, Hitachi, Ltd.
M. Kawashima, Hitachi, Ltd.
pp. 457
Tx7901 Dft (PDF)
Tetsuo Kamada, Toshiba Corporation Semiconductor Company
pp. 458
Toshinobu Ono, NEC Corporation
Akira Kozawa, NEC Software Hokuriku, LTD.
Takashi Kimura, NEC Software Hokuriku, LTD.
Yoshihiro Konno, NEC Corporation
Koji Saga, NEC Corporation
pp. 459
Hisayoshi Hanai, Mitsubishi Electric Corporation
Shinji Yamada, Mitsubishi Electric Corporation
Hisaya Mori, Mitsubishi Electric Corporation
Eisaku Yamashita, Mitsubishi Electric Corporation
Teruhiko Funakura, Mitsubishi Electric Corporation
pp. 460
M. Suzuki, Fujitsu Ltd.
R. Shimizu, Fujitsu Ltd.
N. Naka, Fujitsu Ltd.
K. Nakamura, Fujitsu Ltd.
pp. 461
Tetsuji Kishi, Matsushita Electric Industrial Co,. Ltd.
Mitsuyasu Ohta, Matsushita Electric Industrial Co,. Ltd.
Takashi Taniguchi, Matsushita Electric Industrial Co,. Ltd.
Hiroshi Kadota, Matsushita Electric Industrial Co,. Ltd.
pp. 462
Xiaoqing Wen, SynTest Technologies, Inc.
Hsin-Po Wang, SynTest Technologies, Inc.
pp. 463
Poster Session 2: Practical Ideas from Universities
Shiyi Xu, Shanghai University
pp. 468
Tsung-Chu Huang, National Cheng Kung University
Kuen-Jong Lee, National Cheng Kung University
pp. 470
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