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- ATS
- 2001
- 10th Asian Test Symposium (ATS'01)
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10th Asian Test Symposium (ATS'01) Kyoto, Japan November 19-November 21 ISBN: 0-7695-1378-6 Table of Contents
 | Plenary Session: Keynote Address |
| Session 1A: Design for Testability - Chair: Ermenfried Prochaska, Fachhochschule Heilbronn, Germany |
Yi Xu, Tsinghua University pp. 17
| Session 1B: Fault Modeling for Memories - Chair: Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan |
Said Hamdioui, Intel Corporation and Delft University of Technology pp. 37
| Session 1C: Diagnosis Session - Chair: Shiyi Xu, Shanghai University, China |
| Session 2A: ATPG - Chair: Christian Landrault, LIRMM, France |
| Session 2B: Embedded Memory Test - Chair: Yervant Zorian, Logic Vision, Inc., USA |
| Session 2C: IDDQ and Diagnosis Test - Chair: Hiroshi Yokoyama, Akita University, Japan |
| Session 3A: Test Compaction - Chair: Toshinori Hosokawa, Semiconductor Technology Academic Research Center, Japan |
| Session 3B: Pattern Generation for Memory Test - Chair: Tetsuo Tada, Mitsubishi Electric Corporation, Japan |
R.-L. Jiang, Vanguard International Semiconductor Corporation
J.-W. Hsia, Vanguard International Semiconductor Corporation pp. 151
| Session 3C: Virtual Tester and Beam Testing - Chair: Koji Nakamae, Osaka University, Japan |
Norio Kuji, NTT Electronics Co. and NTT Telecommunications Energy Laboratories
Takako Ishihara, NTT Electronics Co. and NTT Telecommunications Energy Laboratories pp. 179
| Session 4A: SoC Test Access Mechanism - Chair: Hiroshi Date, ABEL Systems Inc., Japan |
| Session 4B: RTL ATPG - Chair: Jacob A. Abraham, University of Texas at Austin, USA |
| Session 4C: Delay Test - Chair: Jacob Savir, New Jersey Institute of Technology, USA |
| Session 5A: SoC Test Scheduling - Chair: Prab Varma, Veritable Inc., USA |
| Session 5B: FSM Test - Chair: Hiroshi Takahashi, Ehime University, Japan |
A. Walker, North Carolina A&T State University pp. 273
Samir Roy, Kalyani Government Engineering College pp. 285
| Session 5C: Online Testing and Fault Injection line - Chair: Masahiro Tsunoyama, Niigata Institute of Technology, Japan |
| Session 6A: Advances in BIST - Chair: Kazuhiko Iijima, Logic Vision, Inc., Japan |
| Session 6B: Analog Test - Chair: Yasuo Furukawa, Advantest Corporation, Japan |
Zhen Guo, New Jersey Institute of Technology pp. 338
| Session 6C: Fault Tolerance - Chair: Hideo Ito, Chiba University, Japan |
| Session 7A: Various Ideas for BIST - Chair: Tokumi Yokohira, Okayama University, Japan |
| Session 7B: Analog/Mixed Signal Test - Chair: Michel Renovell, LIRMM, France |
| Session 7C: Verification - Chair: Kiyoharu Hamaguchi, Osaka University, Japan |
| Poster Session 1: DFT Application to Real Chips |
| Poster Session 2: Practical Ideas from Universities | Usage of this product signifies your acceptance of the Terms of Use.
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