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Ninth Asian Test Symposium (ATS'00)
Taipei, Taiwan
December 04-December 06
ISBN: 0-7695-0887-1
Table of Contents
Reviewers (PDF)
pp. xxiii
Keynote Address I
Keynote Address II
Industry Session I: CAD Tools on Testing, Chair: Jing-Yang Jou, National Chiao Tung University, Taiwan
Hsin-Po Wang, SynTest Technols. Inc., Taiwan
J. Turino, SynTest Technols. Inc., Taiwan
pp. 6
DFT closure (Abstract)
F. Hayat, Synopsis Inc., Mountain View, CA, USA
T.W. Williams, Synopsis Inc., Mountain View, CA, USA
R. Kapur, Synopsis Inc., Mountain View, CA, USA
D. Hsu, Synopsis Inc., Mountain View, CA, USA
pp. 8
Industry Session II: Taiwan Test Industry: Value Added Testing in the New Millennium, Chair: Chung-Len Lee, National Chiao Tung University, Taiwan
(PDF)
pp. 13
Panel I
Panel II
Session A1: Analog & Mixed Signal Test I, Chair: Kiyoshi Furuya, Chuo University, Japan
S. Cherubal, Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee, Georgia Inst. of Technol., Atlanta, GA, USA
pp. 19
Jun-Weir Lin, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung-Len Lee, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chau-Chin Su, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jwu-E Chen, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 25
G. Huertas, Inst. de Microelectron., Seville Univ., Spain
D. Vazquez, Inst. de Microelectron., Seville Univ., Spain
E. Peralias, Inst. de Microelectron., Seville Univ., Spain
A. Rueda, Inst. de Microelectron., Seville Univ., Spain
J.L. Huertas, Inst. de Microelectron., Seville Univ., Spain
pp. 31
K.Y. Ko, Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
M.W.T. Wong, Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
pp. 39
Session A2: Memory Built-in Self-Test and Self-Diagnosis, Chair: Ad J. van de Goor, Delft University of Technology, The Netherlands
Chih-Wea Wang, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chi-Feng Wu, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jin-Fu Li, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
T. Teng, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
K. Chiu, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Hsiao-Ping Lin, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 45
J.R. Huang, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
C.K. Ong, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
K.T. Cheng, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
C.W. Wu, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 51
Chen-Huan Chiang, Lucent Technols., Princeton, NJ, USA
S.K. Gupta, Lucent Technols., Princeton, NJ, USA
pp. 58
Sying-Jyan Wang, Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
Chen-Jung Wei, Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
pp. 66
Session B1: Analog & Mixed Signal Test II, Chair: M.D. Shieh, National Yunlin Technical University, Taiwan
Wooyoung Choi, Minnesota Univ., Minneapolis, MN, USA
R. Harjani, Minnesota Univ., Minneapolis, MN, USA
B. Vinnakota, Minnesota Univ., Minneapolis, MN, USA
pp. 72
L. Carro, Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
E. Cota, Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
M. Lubaszewski, Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
Y. Bertrand, Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
F. Azais, Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
M. Renovell, Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 78
M. Worsman, Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
M.W.T. Wong, Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
Y.S. Lee, Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
pp. 84
Yin-Chao Huang, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung-Len Lee, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jun-Weir Lin, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jwu-E Chen, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chau-Chin Su, Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 90
Session B2: Fault Simulation & Timing Simulation, Chair: Kazumi Hatayama, Hitachi, Japan
Liang-Chi Chen, Dept. of Electr. Eng.-Systems, Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta, Dept. of Electr. Eng.-Systems, Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer, Dept. of Electr. Eng.-Systems, Univ. of Southern California, Los Angeles, CA, USA
pp. 102
I. Pomeranz, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
S.M. Reddy, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 108
S. Sur-Kolay, Indian Stat. Inst., Calcutta, India
M. Roncken, Indian Stat. Inst., Calcutta, India
K. Stevens, Indian Stat. Inst., Calcutta, India
P.P. Chaudhuri, Indian Stat. Inst., Calcutta, India
R. Roy, Indian Stat. Inst., Calcutta, India
pp. 114
A. Keshk, Grad. Sch. of Eng., Osaka Univ., Japan
Y. Miura, Grad. Sch. of Eng., Osaka Univ., Japan
K. Kinoshita, Grad. Sch. of Eng., Osaka Univ., Japan
pp. 120
S. Polonsky, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. McManus, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D. Knebel, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S. Steen, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Sanda, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 125
Fringe Meeting
SoC Testing & P1500 Standard
Session C1: Fault Analysis I, Chair: Shiyi Xu, Shanghai University of Science and Technology, China
S. Kajihara, Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
T. Shimono, Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
I. Pomeranz, Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
S.M. Reddy, Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
pp. 139
Lijian Li, Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Xiaoyang Yu, Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Cheng-Wen Wu, Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Yinghua Min, Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 145
J. Dworak, Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
M.R. Grimaila, Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
B. Cobb, Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
T.-C. Wang, Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
L.-C. Wang, Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
M.R. Mercer, Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
pp. 151
Session C2: Test Generation I, Chair: Yukihiro Iguchi, Meiji University, Japan
A. Giani, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Shuo Sheng, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M. Hsiao, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
V.D. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 159
Y. Higami, Ehime Univ., Matsuyama, Japan
Y. Takamatsu, Ehime Univ., Matsuyama, Japan
K. Kinoshita, Ehime Univ., Matsuyama, Japan
pp. 165
E. Gizdarski, Dept. of Comput. Syst., Rousse Univ., Rousse, Bulgaria
H. Fujiwara, Dept. of Comput. Syst., Rousse Univ., Rousse, Bulgaria
pp. 171
Shiyi Xu, Sch. of Comput. Sci. & Eng., Shanghai Univ., China
Wei Cen, Sch. of Comput. Sci. & Eng., Shanghai Univ., China
pp. 179
Session C3: Functional Testing, Chair: Tomoo Inoue, Hiroshima University, Japan
Y. Makris, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
J. Collins, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 185
J. Hirase, Matsushita Electr. Ind. Co. Ltd., Japan
S. Yoshimura, Matsushita Electr. Ind. Co. Ltd., Japan
pp. 191
Rajesh Kannah, ATI Research Silicon Valley Inc, Chennai
C.P. Ravikumar, Indian Institute of Technology, New Delhi
pp. 204
Session D1: Built-in Self-Test I, Chair: Jacob Savir, New Jersey Institute of Technology
T. Masuzawa, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
M. Izutsu, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
H. Wada, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
H. Fujiwara, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
pp. 210
S.L. Lin, Intelligent Micro Inc., San Jose, CA, USA
S. Mourad, Intelligent Micro Inc., San Jose, CA, USA
S. Krishnan, Intelligent Micro Inc., San Jose, CA, USA
pp. 216
Ming-Der Shieh, Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
Hsin-Fu Lo, Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
Ming-Hwa Sheu, Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
pp. 222
Session D2: Software Testing & Test Synthesis, Chair: Wen-Ben Jone, national Chung Cheng University, Taiwan
Xiaowei Li, Dept. of Comput. Sci., Beijing Univ., China
T. Masuzawa, Dept. of Comput. Sci., Beijing Univ., China
H. Fujiwara, Dept. of Comput. Sci., Beijing Univ., China
pp. 229
M. Hirayama, Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
J. Okayasu, Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
T. Yamamoto, Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
O. Mizuno, Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
T. Kikuno, Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
pp. 235
Jin-Cherng Lin, Dept. of Comput. Sci. & Eng., Tatung Univ., Taipei, Taiwan
Pu-Lin Yeh, Dept. of Comput. Sci. & Eng., Tatung Univ., Taipei, Taiwan
pp. 241
Session D3: Embedded-Core Testing, Chair: Douglas Kay, Cisco, USA
Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Cheng-I Huang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 248
Ruofan Xu, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.S. Hsiao, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 254
Session E1: Memory Testing, Chair: Rubin A. Parekhji, TI, India
Ding-Ming Kwai, Taiwan Semicond. Manuf. Co., Taiwan
Hung-Wen Chang, Taiwan Semicond. Manuf. Co., Taiwan
Hung-Jen Liao, Taiwan Semicond. Manuf. Co., Taiwan
Ching-Hua Chiao, Taiwan Semicond. Manuf. Co., Taiwan
Yung-Fa Chou, Taiwan Semicond. Manuf. Co., Taiwan
pp. 268
Yea-Ling Horng, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jing-Reng Huang, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Tsin-Yuan Chang, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 274
Zaid Al-Ars, Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
A.J. van de Goor, Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
pp. 282
Wen-Jer Wu, Cadence Design Syst., Hsin-Chu, Taiwan
Chuan Yi Tang, Cadence Design Syst., Hsin-Chu, Taiwan
pp. 290
D.C. Huang, Dept. of CS&IE, Nat. Chung-Cheng Univ., Taiwan
W.B. Jone, Dept. of CS&IE, Nat. Chung-Cheng Univ., Taiwan
pp. 299
Session E2: Test Generation II, Chair: Christian Landrault, LIRMM, France
Wei-Yu Chen, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 305
B. Liu, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
W.K. Huang, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 311
I. Pomeranz, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
S.M. Reddy, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 317
M. Renovell, LIRMM-UM2, Montpellier, France
J.M. Portal, LIRMM-UM2, Montpellier, France
P. Faure, LIRMM-UM2, Montpellier, France
J. Figueras, LIRMM-UM2, Montpellier, France
Y. Zorian, LIRMM-UM2, Montpellier, France
pp. 323
Y. Morihiro, Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
T. Toneda, Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
pp. 329
Session E3: IDDQ Testing, Chair: Sying-Jyan Wang, National Chung Hsing University, Taiwan
Chih-Wen Lu, Dept. of Electr. Eng., Da Yeh Univ., Taiwan
Chauchin Su, Dept. of Electr. Eng., Da Yeh Univ., Taiwan
Chung Len Lee, Dept. of Electr. Eng., Da Yeh Univ., Taiwan
Jwu-E Chen, Dept. of Electr. Eng., Da Yeh Univ., Taiwan
pp. 338
M. Hashizume, Fac. of Eng., Tokushima Univ., Japan
H. Yotsuyanagi, Fac. of Eng., Tokushima Univ., Japan
M. Ichimiya, Fac. of Eng., Tokushima Univ., Japan
T. Tamesada, Fac. of Eng., Tokushima Univ., Japan
M. Takeda, Fac. of Eng., Tokushima Univ., Japan
pp. 344
T. Maeda, Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita, Dept. of Appl. Phys., Osaka Univ., Japan
pp. 350
Y. Antonioli, Test Eng. Center, Sharp Corp., Nara, Japan
T. Inufushi, Test Eng. Center, Sharp Corp., Nara, Japan
S. Nishikawa, Test Eng. Center, Sharp Corp., Nara, Japan
K. Kinoshita, Test Eng. Center, Sharp Corp., Nara, Japan
pp. 356
T. Shinogi, Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
M. Ushio, Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
T. Hayashi, Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
pp. 362
Session F1: Built-in Self-Test II, Chair: Shianling Wu, Lucent, USA
Wei-Lun Wang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 368
P. Chang, Intel Texas Design Center, Austin, TX, USA
B. Keller, Intel Texas Design Center, Austin, TX, USA
S. Paliwal, Intel Texas Design Center, Austin, TX, USA
pp. 374
A. Hlawiczka, Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
M. Kopec, Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
pp. 380
Lijian Li, Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Yinghua Min, Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 386
Session F2: Testability Analysis and Design for Testability, Chair: Xinghao Chen, IBM, USA
Yin-He Su, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Ching-Hwa Cheng, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Shih-Chieh Chang, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
pp. 392
M. Inoue, Nara Inst. of Sci. & Technol., Japan
E. Gizdarski, Nara Inst. of Sci. & Technol., Japan
H. Fujiwara, Nara Inst. of Sci. & Technol., Japan
pp. 398
M.L. Flottes, Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France
C. Landrault, Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France
A. Petitqueux, Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France
pp. 404
Session F3: Fault Tolerance, Chair: J.C. Frank Lien, Actel, USA
A. Doumar, Dept. of Inf. & Image Sci., Chiba Univ., Japan
H. Ito, Dept. of Inf. & Image Sci., Chiba Univ., Japan
pp. 411
F. Vargas, Dept. of Electr. Eng., Catholic Univ., Porto Alegre, Brazil
A. Amory, Dept. of Electr. Eng., Catholic Univ., Porto Alegre, Brazil
pp. 417
N. Kamiura, Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
T. Kodera, Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
N. Matsui, Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
pp. 423
Session G1: Fault Analysis II, Chair: Mike Wong, Hong Kong Polytechnic University, Hong Kong
Ching-Hwa Cheng, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Wen-Ben Jone, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Jinn-Shyan Wang, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Shih-Chieh Chang, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
pp. 435
E. MacDonald, Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
N.A. Touba, Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
pp. 441
Session G2: Low-Power Testing, Chair: C.P. Ravikumar, Indian Institute of Technology, India
Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Tsung-Chu Haung, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Jih-Jeen Chen, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 453
P. Girard, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
L. Guiller, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch, Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 459
Session G3: Self-Checking Circuits and Concurrent Fault Detection, Chair: Yinghua Min, Academia Sinica, China
M.J. Liebelt, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Cheng-Chew Lim, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
pp. 472
J. Savir, Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 478
I. Bayraktaroglu, California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu, California Univ., San Diego, La Jolla, CA, USA
pp. 484
Tutorial 1
Tutorial 2
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