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Ninth Asian Test Symposium (ATS'00)
Test generation for crosstalk-induced faults: framework and computational results
Taipei, Taiwan
December 04-December 06
ISBN: 0-7695-0887-1
ASCII Text
x 
 
Wei-Yu Chen, S.K. Gupta, M.A. Breuer, "Test generation for crosstalk-induced faults: framework and computational results," 2012 IEEE 21st Asian Test Symposium, pp. 305, Ninth Asian Test Symposium (ATS'00), 2000.
 
 
BibTex
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@article{ 10.1109/ATS.2000.893641,
author = {Wei-Yu Chen and S.K. Gupta and M.A. Breuer},
title = {Test generation for crosstalk-induced faults: framework and computational results},
journal ={2012 IEEE 21st Asian Test Symposium},
volume = {0},
year = {2000},
issn = {1081-7735},
pages = {305},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893641},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - 2012 IEEE 21st Asian Test Symposium
TI - Test generation for crosstalk-induced faults: framework and computational results
SN - 1081-7735
SP
EP
A1 - Wei-Yu Chen,
A1 - S.K. Gupta,
A1 - M.A. Breuer,
PY - 2000
KW - crosstalk; automatic test pattern generation; combinational circuits; integrated logic circuits; integrated circuit testing; vectors; circuit analysis computing; 2-vector test generation; crosstalk-induced faults; technology scaling; clock frequency; noise effects; design effort; debugging effort; circuit performance; pulses; signal speedup; signal slowdown; digital combinational circuits; mixed-signal test generator; XGEN; static values; dynamic signals; transitions; timing information; signal arrival times; rise times; fall times; gate delay; SPICE simulations; accuracy
VL - 0
JA - 2012 IEEE 21st Asian Test Symposium
ER -
 
Wei-Yu Chen, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer, Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Due to technology scaling and increasing clock frequency, problems due to noise effects are leading to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk-induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times and gate delay. In this paper, we first discuss the general framework of the test generation algorithm followed by computational results. A comparison of our results with SPICE simulations confirms the accuracy of this approach.
Index Terms:
crosstalk; automatic test pattern generation; combinational circuits; integrated logic circuits; integrated circuit testing; vectors; circuit analysis computing; 2-vector test generation; crosstalk-induced faults; technology scaling; clock frequency; noise effects; design effort; debugging effort; circuit performance; pulses; signal speedup; signal slowdown; digital combinational circuits; mixed-signal test generator; XGEN; static values; dynamic signals; transitions; timing information; signal arrival times; rise times; fall times; gate delay; SPICE simulations; accuracy
Citation:
Wei-Yu Chen, S.K. Gupta, M.A. Breuer, "Test generation for crosstalk-induced faults: framework and computational results," ats, pp.305, Ninth Asian Test Symposium (ATS'00), 2000
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