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Ninth Asian Test Symposium (ATS'00)
Memory test time reduction by interconnecting test items
Taipei, Taiwan
December 04-December 06
ISBN: 0-7695-0887-1
Wen-Jer Wu, Cadence Design Syst., Hsin-Chu, Taiwan
Chuan Yi Tang, Cadence Design Syst., Hsin-Chu, Taiwan
The idea is to interconnect test items to reuse memory states left from the previous test item for saving initialization and verification sequences. Meanwhile, signal settling time of the tester between two consecutive test items being applied can also be minimized since all test items are connected together into a continuous one. The interconnection problem is transformed to the Rural Chinese Postman (RCP) problem. The RCP problem is a famous NP-hard problem, one way to solve the RCP problem is by modeling as an integer linear programming (ILP) model. However, in the worst case, it will incur an exponential number of constraints; therefore, it is not suitable for practical usage. Instead of putting all constraints at once, we generate and solve a number of successive ILP models with the smaller number of constraints. The total numbers of iterations and constraints applied to solve ILP models are analyzed and compared.
Index Terms:
integrated memory circuits; integrated circuit testing; linear programming; integer programming; graph theory; memory test time reduction; test items interconnection; initialization sequences; verification sequences; signal settling time; interconnection problem; rural Chinese postman problem; NP-hard problem; integer linear programming model; successive ILP models; constraints; iterations
Citation:
Wen-Jer Wu, Chuan Yi Tang, "Memory test time reduction by interconnecting test items," ats, pp.290, Ninth Asian Test Symposium (ATS'00), 2000
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