Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits

A. Keshk; Y. Miura; K. Kinoshita

doi:10.1109/ATS.2000.893613

A
ATS
2000
Ninth Asian Test Symposium (ATS'00)
Abstract - Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits

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Ninth Asian Test Symposium (ATS'00)

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits

Taipei, Taiwan

December 04-December 06

ISBN: 0-7695-0887-1

	ASCII Text	x
	A. Keshk, Y. Miura, K. Kinoshita, "Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits," 2012 IEEE 21st Asian Test Symposium, pp. 120, Ninth Asian Test Symposium (ATS'00), 2000.

	BibTex	x
	@article{ 10.1109/ATS.2000.893613, author = {A. Keshk and Y. Miura and K. Kinoshita}, title = {Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits}, journal ={2012 IEEE 21st Asian Test Symposium}, volume = {0}, year = {2000}, issn = {1081-7735}, pages = {120}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893613}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - 2012 IEEE 21st Asian Test Symposium TI - Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits SN - 1081-7735 SP EP A1 - A. Keshk, A1 - Y. Miura, A1 - K. Kinoshita, PY - 2000 KW - logic testing; CMOS digital integrated circuits; fault location; circuit oscillations; integrated circuit testing; logic testing; bridging fault; CMOS circuits; test vector; transistor level networks; feedback oscillation; Byzantine General's problems; logic threshold; fault coverage VL - 0 JA - 2012 IEEE 21st Asian Test Symposium ER -

A. Keshk, Grad. Sch. of Eng., Osaka Univ., Japan

Y. Miura, Grad. Sch. of Eng., Osaka Univ., Japan

K. Kinoshita, Grad. Sch. of Eng., Osaka Univ., Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893613

This paper presents an efficient procedure to improve logic testing for bridging faults (BF) in CMOS circuits. A unified procedure is presented that extracts the test vector from transistor level networks, which will reduce the occurrence of intermediate voltage that leads to Byzantine General's problems and feedback oscillation. By using this procedure according to fault location, the fault coverage of logic testing will increase without using both simulation and a complex calculation for predicting bridging voltage or logic threshold of the driven gates.

Index Terms:

logic testing; CMOS digital integrated circuits; fault location; circuit oscillations; integrated circuit testing; logic testing; bridging fault; CMOS circuits; test vector; transistor level networks; feedback oscillation; Byzantine General's problems; logic threshold; fault coverage

Citation:

A. Keshk, Y. Miura, K. Kinoshita, "Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits," ats, pp.120, Ninth Asian Test Symposium (ATS'00), 2000

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