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Eighth Asian Test Symposium (ATS'99)
Shanghai, China
November 16-November 18
ISBN: 0-7695-0315-2
Table of Contents
Plenary Session: Keynote Address
Built-In Self-Test Past, Present and Future
Session 1A: ATPG Related Approaches I, Chair: Christian Landrault, LIRMM, France
Satoshi Ohtake, Nara Institute of Science and Technology
Michiko Inoue, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 5
Junichi Hirase, Matsushita Electric Industrial Co., Ltd
Shinichi Yoshimura, Matsushita Electric Industrial Co., Ltd
Tomohisa Sczaki, Matsushita Electric Industrial Co., Ltd
pp. 13
Seiji Kajihara, Kyushu Institute of Technology
Atsushi Murakami, Kyushu Institute of Technology
Tomohisa Kaneko, Kyushu Institute of Technology
pp. 20
Session 1B: Delay Fault & Memory Test, Chair: Xinghao Chen, IBM, USA
G. Sidiropoulos, University of Patras and Computer Technology
H.T. Vergos, University of Patras and Computer Technology
D. Nikolos, University of Patras and Computer Technology
pp. 47
Said Hamdioui, Intel Corporation and Delft University of Technology
A. J. van de Goor, Delft University of Technology
pp. 53
Session 2A: ATPG Related Approaches II, Chair: Sreejit Chakravarty, Intel, USA
Zhide Zeng, National University of Defense Technology
Jihua Chen, National University of Defense Technology
Hefeng Cao, National University of Defense Technology
pp. 70
Session 2B: BIST Related Approaches, Chair: Yuejian Wu, Nortel Semiconductor, Canada
P. Girard, Universit? Montpellier II
L. Guiller, Universit? Montpellier II
C. Landrault, Universit? Montpellier II
S. Pravossoudovitch, Universit? Montpellier II
pp. 89
W. Feng, Lucent Technologies
W.K. Huang, Fudan University
F.J. Meyer, Northeastern University
F. Lombardi, Northeastern University
pp. 95
Session 3A: Test Generation, Diagnosis, & Verification, Chair: Hiromi Hiraishi, Kyoto Sangyo University, Japan
Zhide Zeng, National University of Defense Technology
Jihua Chen, National University of Defense Technology
Pengxia Liu, National University of Defense Technology
pp. 133
Session 3B: IDDQ Test, Chair: Dajin Wang, University of Montclair, USA
Junichi Hirase, Matsushita Electric Industrial Co., Ltd
Naoki Shindou, Matsushita Electric Industrial Co., Ltd
Kouji Akahori, Matsushita Electronics Industrial Co., Ltd
pp. 153
Session 4A: Sequential Circuit Test, Chair: Serge Demidenko, Massey University, New Zealand
Toshinori Hosokawa, Matsushita Electric Industrial Co., Ltd.
Toshihiro Hiraoka, Matsushita Electric Industrial Co., Ltd.
Tomoo Inoue, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 192
Session 4B: Fault-Tolerant & Diagnosis, Chair: Xiaozhong Yang, Harbin Institute of Technology, China
Yasuyuki Taniguchi, Himeji Institute of Technology
Naotake Kamiura, Himeji Institute of Technology
Yutaka Hata, Himeji Institute of Technology
Nobuyuki Matsui, Himeji Institute of Technology
pp. 203
Session 5A: Analog Circuits Test, Chair: Chung-Len Lee, National Chiao Tung University, Taiwan
Abdelhakim Khouas, University of Pierre et Marie Curie
Mohamed Dessouky, University of Pierre et Marie Curie
Anne Derieux, University of Pierre et Marie Curie
pp. 227
Chauchin Su, National Central University
Yue-Tsang Chen, National Central University
Chung-Len Lee, National Chiao Tung University
pp. 233
Sam Huynh, University of Washington
Jinyan Zhang, University of Washington
Seongwon Kim, University of Washington
Giri Devarayanadurg, University of Washington
Mani Soma, University of Washington
pp. 239
Session 5B: (Special Session) Railway Signaling Software Testing, Chair: Yinghua Min, ICT of China, China
Session 6A: DFT, Chair: Kiyoshi Furuya, Chuo University, Japan
Debesh Kumar Das, Jadavpur University
Satoshi Ohtake, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 263
Abhijit Jas, University of Texas at Austin
Kartik Mohanram, University of Texas at Austin
Nur A. Touba, University of Texas at Austin
pp. 275
Session 6B: Software Test & Verification, Chair: Kuen-Jong Lee, National Cheng Kung University, Taiwan
Shyue-Kung Lu, Fu Jen Catholic University
Tsung-Ying Lee, Fu Jen Catholic University
Cheng-Wen Wu, National Tsing Hua University
pp. 301
Session 7A: Scan & Boundary Scan, Chair: T.W. Williams, Synopsys, Inc.
Tomoya Takasaki, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
Tomoo Inoue, Hiroshima City University
pp. 309
Zulan Huang, Harbin Institute of Technology
Yizheng Ye, Harbin Institute of Technology
Zhigang Mao, Harbin Institute of Technology
pp. 327
Session 7B: (Special Session) Beam Testing in Japan, Chair: Hiromu Fujioka, Osaka University, Japan
Reisuke Shimoda, Matsushita Electric Industrial Co., Ltd.
Takaki Yoshida, Matsushita Electric Industrial Co., Ltd.
Masafumi Watari, Matsushita Electric Industrial Co., Ltd.
Yasuhiro Toyota, Matsushita Electric Industrial Co., Ltd.
Kiyokazu Nishi, Matsushita Electric Industrial Co., Ltd.
Akira Motohara, Matsushita Electric Industrial Co., Ltd.
pp. 347
Session 8A: FPGA Test, Chair: Hideo Fujiwara, Nara Institute of Science & Technology, Japan
Session 8B: (Special Session) Beam Testing in Japan, Chair: Kiyoshi Nikawa, NEC, Japan
Yoichi Ose, Hitachi, Ltd., Hitachinaka, Japan
Makoto Ezumi, Hitachi, Ltd., Hitachinaka, Japan
Hideo Todokoro, Hitachi, Ltd., Hitachinaka, Japan
pp. 383
Panel Session 1
In Nanometer Technology, How to Test?
Panel Session 2
Difference & Unity between Hardware & Software Testing
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