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Seventh Asian Test Symposium (ATS'98)
Singapore
December 02-December 04
ISBN: 0-8186-8277-9
Table of Contents
Panel Discussion 2: Testing Embedded Memories: Is BIST the Ultimate Solution?, Chair: C.W. Wu, National Tsiang Hua University, Taiwan
Session 3C: Boundary Scan & Interconnect Testing, Chair: S. Yano, Kochi University of Technology, Japan
Reviewers (PDF)
pp. xviii
Plenary Session: Keynote Address, Chair: V. Agrawal, AT&T Bell Labs, USA
Session 1A: BIST I, Chair: C. Landrault, LIRMM, France
Session 1B: High-Level Synthesis, Chair: B. Courtois, TIMA-INPG, France
M.L. Flottes, Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier
R. Pires, Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier
B. Rouzeyre, Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier
pp. 46
Session 1C: Delay Testing, Chair: E. Weis, Chip Eye Technology, Israel
Zhongcheng Li, Chinese Academy of Sciences
Yinghua Min, Chinese Academy of Sciences
Robert K. Brayton, University of California at Berkeley
pp. 76
Huawei Li, Chinese Academy of Sciences
Zhongcheng Li, Chinese Academy of Sciences
Yinghua Min, Chinese Academy of Sciences
pp. 96
Session 2A.1: Fault Modeling & Simulation, Chair: C.-L. Lee, National Chiao Tung University, Taiwan
S.M. Aziz, Bangladesh University of Engineering &Technology
J. Kamruzzaman, Bangladesh University of Engineering &Technology
pp. 119
Session 2A.2: Software Testing, Chair: C. Messom, Dubai Polytechnic, OAE
Haiying Tu, Shanghai Tiedao University
Fangmei Wu, Shanghai Tiedao University
Xiaoxu Ren, Shanghai Tiedao University
pp. 126
Session 2B: Current Testing, Chair: C.V. Jagadish, DVS Technology, Singapore
Session 2C: Test Engineering, Chair: W. Moorhead, Teradyne, Singapore
Peng-Cheng Koo, Siemens Components Private Limited
San-Liek Pang, Siemens Components Private Limited
pp. 160
Kin Wee Choo, Data Storage Institute
Guoxiao Guo, Data Storage Institute
Ben M. Chen, The National University of Singapore
pp. 184
Session 3A: Sequential Circuit Testing, Chair: K. Hatayama, Hitachi, Japan
Session 3B: Defect Analysis & Fault Diagnosis, Chair: M. Wong, Hong Kong Polytechnic University, Hong Kong
Session 4A: FPGA Testing, Chair: M. Jacomet, Biel School of Engineering, Switzerland
Session 4B: On-Line Testing & Fault Tolerance, Chair: S.M. Azis, Bangladesh University of Engineering & Technology, Bangladesh
Session 4C: IDDQ Testing, Chair: H. Tamamoto, Akita University, Japan
Session 5A: Memory Testing, Chair: W. Tan, Texas Instruments, Singapore
Session 5B: Analog & Mixed Signal Test, Chair: B. Kaminska, OPMAXX, USA
Sam Huynh, University of Washington
Seongwon Kim, University of Washington
Mani Soma, University of Washington
Jinyan Zhang, University of Washington
pp. 360
Session 5C: Design Verification, Chair: Y. Iguchi, Yukihiro, Meiji University, Japan
Zhen Guo, Chinese Academy of Space Technology
He Li, Chinese Academy of Space Technology
Shuling Guo, Chinese Academy of Space Technology
Dongsheng Wang, Chinese Academy of Space Technology
pp. 413
Improving Design Robustness with the Aid of Simulation and Statistical Techniques
Session 6A: BIST II, Chair: M. Lubaszewski, University of Porto Alegre, Brazil
P. Girard, Universit? Montpellier II / CNRS
C. Landrault, Universit? Montpellier II / CNRS
V. Moreda, Universit? Montpellier II / CNRS
S. Pravossoudovitch, Universit? Montpellier II / CNRS
A. Virazel, Universit? Montpellier II / CNRS
pp. 435
Session 6B: Sequential Circuit Testing, Chair: H. Fujiwara, Nara Institute of Science & Technology, Japan
Session 6C: Test Program Generation, Chair: Q.-F. Chen, Beijing Institute of Automatic Test Technology, China
Panel Discussion 1: Microsystem Testing: Challenge or Common Knowledge?, Organizer: H.G. Kerkhoff, MESA Research/UT, The Netherlands
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