CSDL - Proceedings A

Program Chair's Message (PDF)

pp. xi

Asian Test Committee (PDF)

pp. xii

The Sixth Asian Test Symposium Committee (PDF)

pp. xiii

Program Committee Members (PDF)

pp. xiv

Reviewers (PDF)

pp. xv

Plenary Session: Keynote Address

Embedded Test and Measurement Critical for Deep Submicron Technology (PDF)

pp. 2

Session 1A: Test Generation I, Chair: J. Savir, New Jersey Institute of Technology, USA

On the Compaction of Test Sets Produced by Genetic Optimization (Abstract)

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 4

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On the Adders with Minimum Tests (Abstract)

Seiji Kajihara, Kyushu Institute of Technology

Tsutomu Sasao, Kyushu Institute of Technology

pp. 10

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Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL (Abstract)

Tsuyoshi Shinogi, Faculty of Engineering, Mie University

Terumine Hayashi, Faculty of Engineering, Mie University

Kazuo Taki, Faculty of Engineering, Kobe University

pp. 16

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An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits (Abstract)

Noroyoshi Itazaki, Applied Physics, Osaka Univ.

Yasutaka Idomoto, Applied Physics, Osaka Univ.

Kozo Kinoshita, Applied Physics, Osaka Univ.

pp. 22

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Session 1B: Design for Testability I, Chair: S.K. Jhajharia, Singapore Polytechnic, Singapore

Guaranteeing Testability in Re-encoding for Low Power (Abstract)

S. Chiusano, Politecnico di Torino

F. Corno, Politecnico di Torino

P. Prinetto, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

pp. 30

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Automatic Testability Analysis of Boards and MCMs at Chip Level (Abstract)

pp. 36

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Design of C-Testable Multipliers Based on the Modified Booth Algorithm (Abstract)

Kwame Osei Boateng, Faculty of Engineering, Ehime University

Hiroshi Takahashi, Faculty of Engineering, Ehime University

Yuzo Takamatsu, Faculty of Engineering, Ehime University

pp. 42

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Testability Prediction for Sequential Circuits Using Neural Network (Abstract)

Shiyi Xu, Shanghai University of Science and Technology

Peter Waignjo, Shanghai University of Science and Technology

Percy G. Dias, Fudan University

Bole Shi, Fudan University

pp. 48

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Session 2A: Test Generation II, Chair: B. Kaminska, OPMAXX, USA

A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits (Abstract)

F. Corno, Politecnico di Torino

P. Prinetto, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

G. Squillero, Politecnico di Torino

pp. 56

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Sequential Test Generation Based on Circuit Pseudo-Transformation (Abstract)

Satoshi Ohtake, Nara Institute of Science and Technology

Tomoo Inoue, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 62

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Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG (Abstract)

F. Corno, Politecnico di Torino

P. Prinetto, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

M. Violante, Politecnico di Torino

pp. 68

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TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits (Abstract)

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 74

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Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits (Abstract)

Session 2B: Fault Tolerance, Chair: N. Kanekawa, Hitachi, Japan

pp. 82

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On fault injection approaches for fault tolerance of feedforward neural networks (Abstract)

T. Ito, Dept. of Comput. Sci., Iwate Univ., Morioka, Japan

I. Takanami, Dept. of Comput. Sci., Iwate Univ., Morioka, Japan

pp. 88

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A concurrent fault-detection scheme for FFT processors (Abstract)

M. Tsunoyama, Niigata Inst. of Technol., Japan

M. Uenoyama, Niigata Inst. of Technol., Japan

T. Kabasawa, Niigata Inst. of Technol., Japan

pp. 94

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Code-Disjoint Circuits for Parity Circuits (Abstract)

Hendrik Hartje, University of Potsdam

Michael Goessel, University of Potsdam

Egor S. Sogomonyan, Russian Academy of Sciences

pp. 100

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Session 3A: Special Session I - Case Studies for DFT Techniques in Japanese Industry, Chair & Coordinator, M. Yoshida, NEC, Japan

Testability Features of R10000 Microprocessor (Abstract)

Junji Mori, Toshiba Corp.

Ben Mathew, Silicon Graphics Inc.

Dave Burns, Silicon Graphics Inc.

Yeuk-Hai Mok, Silicon Graphics Inc.

pp. 108

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Application of a Design for Delay Testability Approach to High Speed Logic LSIs (Abstract)

K. Hatayama, Hitachi Research Laboratory, Hitachi, Ltd.

M. Ikeda, Hitachi Research Laboratory, Hitachi, Ltd.

M. Takakura, Hitachi Engineering, Co. Ltd.

S. Uchiyama, Hitachi Engineering, Co. Ltd.

Y. Sakamoto, Hitachi Information Technology, Co. Ltd.

pp. 112

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An effective fault simulation method for core based LSI (Abstract)

T. Yoshida, Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

R. Shimoda, Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

T. Mizokawa, Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

K. Hirayama, Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

pp. 116

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Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs (Abstract)

Toshinobu Ono, NEC Corporation, ULSI Systems Development Laboratories

Kazuo Wakui, NEC Corporation, ULSI Systems Development Laboratories

Hitoshi Hikima, NEC Corporation, ULSI Systems Development Laboratories

Yoshiyuki Nakamura, NEC Corporation, ULSI Systems Development Laboratories

Masaaki Yoshida, NEC Corporation, ULSI Systems Development Laboratories

pp. 122

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ATREX : Design for Testability System for Mega Gate LSIs (Abstract)

Michiaki Emori, Fujitsu Limited

Junko Kumagai, Fujitsu Limited

Koichi Itaya, Fujitsu Limited

Takashi Aikyo, Fujitsu Limited

Tomoko Anan, Fujitsu Lsi Tecnology Limited

Junichi Niimi, Fujitsu Lsi Tecnology Limited

pp. 126

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Session 3B: Test Technologies, Chair: M. Nishihara, IBM Japan

On energy efficiency of VLSI testing (Abstract)

Cheng-Wen Wu, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

pp. 132

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ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs (Abstract)

Marcel Jacomet, Biel School of Engineering

Roger Waelti, Biel School of Engineering

Lukas Winzenried, Biel School of Engineering

Jaime Perez, Biel School of Engineering

Martin Gysel, Biel School of Engineering

pp. 138

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Computing stress tests for interconnect defects (Abstract)

V. Dabholkar, Motorola Inc., Austin, TX, USA

S. Chakravarty, Motorola Inc., Austin, TX, USA

pp. 143

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Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits (Abstract)

Josep Altet, Universitat Politecnica de Catalunya

Antonio Rubio, Universitat Politecnica de Catalunya

Hideo Tamamoto, Akita University

pp. 149

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A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register (Abstract)

Z.M. Darus, Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia

I. Ahmed, Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia

L. Ali, Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia

pp. 155

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Session 4A: Special Session II - Beam Testing of VLSI Circuits in Japan, Chair: K. Nikawa, NEC, Japan

Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data (Abstract)

Katsuyoshi Miura, Faculty of Engineering, Osaka University

Kohei Nakata, Faculty of Engineering, Osaka University

Koji Nakamae, Faculty of Engineering, Osaka University

Hiromu Fujioka, Faculty of Engineering, Osaka University

pp. 162

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An approach to diagnose logical faults in partially observable sequential circuits (Abstract)

K. Yamazaki, Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

T. Yamada, Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

pp. 168

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Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits (Abstract)

Norio Kuji, NTT System Electronics Laboratories

pp. 174

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Session 4B: Mixed-Signal Test, Chair: C.W. Wu, National Tsing Hua University, Taiwan

A perturbation based fault modeling and simulation for mixed-signal circuits (Abstract)

N. Ben-Hamida, OPMAXX Inc., Beaverton, OR., USA

K. Saab, OPMAXX Inc., Beaverton, OR., USA

D. Marche, OPMAXX Inc., Beaverton, OR., USA

B. Kaminska, OPMAXX Inc., Beaverton, OR., USA

pp. 182

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Static Testing of ADCs Using Wavelet Transforms (Abstract)

Takahiro Yamaguchi, Advantest Laboratories Ltd.

pp. 188

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Analog signal metrology for mixed signal ICs (Abstract)

Chauchin Su, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Yi-Ren Cheng, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Yue-Tsang Chen, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Shing Tenchen, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

pp. 194

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Session 5A: Special Session III - Novel Beam Testing Techniques in Japan, Chair: M. Miyoshi, Toshiba, Japan

A New Auto-Focus Method in Critical Dimension Measurement SEM (Abstract)

F. Komatsu, Toshiba Corp.

H. Motoki, Toshiba Corp.

M. Miyoshi, Toshiba Corp.

pp. 202

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Novel Optical Probing System for Quarter-micron VLSI Circuits (Abstract)

K. Ozaki, Fujitsu Laboratories Ltd.

H. Sekiguchi, Fujitsu Laboratories Ltd.

S. Wakana, Fujitsu Laboratories Ltd.

Y. Goto, Fujitsu Laboratories Ltd.

Y. Umehara, Advantest Corporation

J. Matsumoto, Advantest Corporation

pp. 208

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New Capabilities of OBIRCH Method for Fault Localization and Defect Detection (Abstract)

Kiyoshi Nikawa, NEC Corporation

Shoji Inoue, NEC Corporation

pp. 214

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Session 5B: Decision Diagrams and Logic Optimization; Coordinator: H. Fujioka, Osaka University, Japan

On Acceleration of Logic Circuits Optimization Using Implication Relations (Abstract)

Hideyuki Ichihara, Osaka University

Kozo Kinoshita, Osaka University

pp. 222

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A variable reordering method for fast optimization of binary decision diagrams (Abstract)

Moon-Bae Song, Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea

Hoon Chang, Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea

pp. 228

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On Decomposition of Kleene TDDs (Abstract)

Yukihiro Iguchi, Meiji University

Tsutomu Sasao, Kyushu Institute of Technology

Munehiro Matsuura, Kyushu Institute of Technology

pp. 234

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Session 6A: FPGA Test, Chair: S. Xu, Shanghai University of Science and Technology, China

Testing for the programming circuit of LUT-based FPGAs (Abstract)

H. Michinishi, Dept. of Inf. Technol., Okayama Univ., Japan

T. Yokohira, Dept. of Inf. Technol., Okayama Univ., Japan

T. Okamoto, Dept. of Inf. Technol., Okayama Univ., Japan

T. Inoue, Dept. of Inf. Technol., Okayama Univ., Japan

H. Fujiwara, Dept. of Inf. Technol., Okayama Univ., Japan

pp. 242

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A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs (Abstract)

W.K. Huang, Fudan University

M.Y. Zhang, Fudan University

F.J. Meyer, Texas A&M University

F. Lombardi, Texas A&M University

pp. 248

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Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA (Abstract)

M. Renovell, LIRMM-UMII

J.M. Portal, LIRMM-UMII

J. Figueras, Universitat Polytechnica de Catalunya

Y. Zorian, Logic Vision Inc.

pp. 254

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Session 6B: Software Test, Chair: T. Yoneda, Tokyo Institute of Technology, Japan

An Algorithm for All-du-path Testing Coverage of Shared Memory Parallel Programs (Abstract)

C.-S. D. Yang, University of Delaware

L. L. Pollock, University of Delaware

pp. 263

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Estimating the Number of Faults using Simulator based on Generalized Stochastic Petri-Net Model (Abstract)

Osamu Mizuno, Osaka University

Shinji Kusumoto, Osaka University

Tohru Kikuno, Osaka University

Yasunari Takagi, OMRON Corporation, Japan

Keishi Sakamoto, OMRON Corporation, Japan

pp. 269

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Session 7A: Diagnosis, Chair: Y. Min, Chinese Academy of Sciences, China

On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs (Abstract)

Tomoo Inoue, Nara Institute of Science and Technology

Satoshi Miyazaki, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 276

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Fault Diagnosis for Static CMOS Circuits (Abstract)

Wen Xiaoqing, Dept. of Information Engineering, Akita 010, Japan

pp. 282

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Fault diagnosis of odd-even sorting networks (Abstract)

Chih Wei Hu, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Chung Len Lee, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Wen Ching Wu, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

J.E. Chen, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

pp. 288

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Session 7B: Design for Testability II, Chair: A. Ivanov, University of British Columbia, Canada

On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers (Abstract)

Jacob Savir, New Jersey Institute of Technology

pp. 296

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Test Compaction in a Parallel Access Scan Environment (Abstract)

Sandeep Bhatia, Duet Technologies Inc.

Prab Varma, Duet Technologies Inc.

pp. 300

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A Partial Scan Design Method Based on n-Fold Line-up Structures (Abstract)

pp. 306

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Session 8A: Delay Test, Chair: C. Landrault, LIRMM, France

On the capability of delay tests to detect bridges and opens (Abstract)

S. Chakravarty, Intel Corp., Santa Clara, CA, USA

pp. 314

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A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits (Abstract)

Hiroshi Takahashi, Ehime University

Kwame Osei Boateng, Ehime University

Yuzo Takamatsu, Ehime University

Toshiyuki Matsunaga, NEC Corporation

pp. 320

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Memory Efficient ATPG for Path Delay Faults (Abstract)

Wangning Long, Tsinghua University

Shiyuan Yang, Tsinghua University

Zhongcheng Li, Chinese Academy of Science

Yinghua Min, Chinese Academy of Science

pp. 326

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Design of delay-verifiable combinational logic by adding extra inputs (Abstract)

Xiaoming Yu, Inst. of Comput. Technol., Acad. Sinica, Beijing, China

Yinghua Min, Inst. of Comput. Technol., Acad. Sinica, Beijing, China

pp. 332

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Session 8B: Built-in Self-Test I, Chair: K. Iwasaki, Tokyo Metropolitan University, Japan

BIST testability enhancement using high level test synthesis for behavioral and structural designs (Abstract)

Kowen Lai, Rockwell Semicond. Syst., Newport Beach, CA, USA

C.A. Papachristou, Rockwell Semicond. Syst., Newport Beach, CA, USA

M. Baklashov, Rockwell Semicond. Syst., Newport Beach, CA, USA

pp. 338

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On Chip Weighted Random Patterns (Abstract)

Jacob Savir, New Jersey Institute of Technology

pp. 343

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Random Pattern Testable Design with Partial Circuit Duplication (Abstract)

Hiroshi Yokoyama, Mining College, Akita University

Xiaoqing Wen, Mining College, Akita University

Hideo Tamamoto, Mining College, Akita University

pp. 353

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Accelerated Test Points Selection Method for Scan-Based BIST (Abstract)

Michinobu Nakao, Hitachi Research Laboratory, Hitachi, Ltd.

Kazumi Hatayama, Hitachi Research Laboratory, Hitachi, Ltd.

Isao Higashi, General Purpose Computer Division, Hitachi, Ltd.,

pp. 359

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Session 9A: Current Testing, Chair: J.E. Chen, Chung-Hua Polytechnic Institute, Taiwan

Power supply current monitoring techniques for testing PLLs (Abstract)

M. Dalmia, Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada

A. Ivanov, Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada

S. Tabatabaei, Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada

pp. 366

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Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates (Abstract)

Masaki Hashizume, The Univ. of Tokushima

Toshimasa Kuchii, The Univ. of Tokushima

Takeomi Tamesada, The Univ. of Tokushima

pp. 372

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IDDT Testing (Abstract)

Yinghua Min, Institute of Computing Technology, Chinese Academy of Sciences

Zhuxing Zhao, Institute of Computing Technology, Chinese Academy of Sciences

Zhongcheng Li, Institute of Computing Technology, Chinese Academy of Sciences

pp. 378

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Built-in current sensor designs based on the bulk-driven technique (Abstract)

Tsung-Chu Huang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Min-Cheng Huang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

pp. 384

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Session 9B: Built-in Self-Test II, Chair: T. Tada, Mitsubishi, Japan

Test Length for Random Testing of Sequential Machines Application to RAMs (Abstract)

René David, INPG-UJF-CNRS

pp. 392

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Built-In Self-Test for Multi-Port RAMs (Abstract)

Yuejian Wu, Northern Telecom., Ltd.

Sanjay Gupta, Northern Telecom., Ltd.

pp. 398

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An extended march test algorithm for embedded memories (Abstract)

Gang-Min Park, Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea

Hoon Chang, Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea

pp. 404

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Low Cost Bist for Edac Circuits (Abstract)

Dariusz Badura, Silesian University of Katowice

Andrzej Hlawiczka, Silesian Technical University of Gliwice

pp. 410

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Author Index (PDF)

pp. 416

ATS'98 Call-for-Papers (PDF)

pp. 418