CSDL - Proceedings A

Program Chair's Message (PDF)

pp. xi

Technical Committee (PDF)

pp. xii

ATS Chairs and Liaison Officers (PDF)

pp. xiv

Program Committee (PDF)

pp. xvi

Reviewers (PDF)

pp. xviii

Plenary Session: Keynote Speech

"Challenges in Testing" (PDF)

Sudhakar M. Reddy

pp. 2

Session 1A: Test Pattern Generation

Redundancy Identification Using Transitive Closure (Abstract)

Vishwani D. Agrawal, Bell Labs Lucent Technologies

Michael L. Bushnell, Rutgers University

Qing Lin, Sun Microsystems

pp. 4

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Invalid State Identification for Sequential Circuit Test Generation (Abstract)

Hsing-Chung Liang, National Chiao Tung University

Chung Len Lee, National Chiao Tung University

Jwu E Chen, National Chiao Tung University

pp. 10

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On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem (Abstract)

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 16

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Hierarchical Test Generation with Built-In Fault Diagnosis (Abstract)

Dirk Stroobandt, University of Ghent

Jan Van Campenhout, University of Ghent

pp. 22

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Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors (Abstract)

J.T. van der Linden, Delft University of Technology

M.H. Konijnenburg, Delft University of Technology

A.J. van de Goor, Delft University of Technology

pp. 29

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E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation (Abstract)

pp. 34

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Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust Testing (Abstract)

pp. 42

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Session 1B: Board and System-Level Test

Hybrid Pin Control Using Boundary-Scan And Its Applications (Abstract)

Wuudiann Ke, Lucent Technologies Bell Labs.

pp. 44

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Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module (Abstract)

Jin-Hua Hong, National Tsing Hua University

Chung-Hung Tsai, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 50

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Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems (Abstract)

Po-Ching Hsu, Holtek Microelectron. Inc., Hsinchu, Taiwan

Sying-Jyan Wang, Holtek Microelectron. Inc., Hsinchu, Taiwan

pp. 56

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Syndrome Simulation And Syndrome Test For Unscanned Interconnects (Abstract)

Chauchin Su, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Shyh-Shen Hwang, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Shyh-Jye Jou, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Yuan-Tzu Ting, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

pp. 62

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A Test Methodology for Interconnect Structures of LUT-based FPGAs (Abstract)

Hiroyuki Michinishi, Okayama University

Tokumi Yokohira, Okayama University

Takuji Okamoto, Okayama University

Tomoo Inoue, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 68

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Testable Design and Testing of MCMs Based on Multifrequency Scan (Abstract)

Wang-Dauh Tseng, National Chiao Tung University

Kuochen Wang, National Chiao Tung University

pp. 75

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Session 2A: Design for Testability

A Consistent Scan Design System for Large-Scale ASICs (Abstract)

Yoshihiro Konno, NEC Corporation

Kazushi Nakamura, NEC Corporation

Tatsushige Bitoh, NEC Corporation

Koji Saga, NEC Corporation

Seiken Yano, NEC Corporation

pp. 82

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A Design for testability Method Using RTL Partitioning (Abstract)

Toshinori Hosokawa, Matsushita Electric Industrial Co., Ltd.

Kenichi Kawaguchi, Matsushita Electric Industrial Co., Ltd.

Mitsuyasu Ohta, Matsushita Electric Industrial Co., Ltd.

Michiaki Muraoka, Matsushita Electric Industrial Co., Ltd.

pp. 88

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Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique (Abstract)

Yoshinobu Higami, Osaka University

Seiji Kajihara, Osaka University

Kozo Kinoshita, Osaka University

pp. 94

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Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults (Abstract)

Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Jing-Jou Tang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Tsung-Chu Huang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Cheng-Liang Tsai, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

pp. 100

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Session 2B: Concurrent Error Detection and Fault Tolerance

On Design of Fail-Safe Cellular Arrays (Abstract)

Naotake Kamiura, Himeji Institute of Technology

Yutaka Hata, Himeji Institute of Technology

Kazuharu Yamato, Himeji Institute of Technology

pp. 107

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Concurrent Error Detection and Fault Location in a Fast ATM Switch (Abstract)

Yoon-Hwa Choi, Hongik University, Seoul, Korea

Pong-Gyou Lee, Hongik University, Seoul, Korea

pp. 113

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Formal Verification Of Self-Testing Properties Of Combinational Circuits (Abstract)

K. Kawakubo, Fac. of Eng., Fukuyama Univ., Japan

K. Tanaka, Fac. of Eng., Fukuyama Univ., Japan

H. Hiraishi, Fac. of Eng., Fukuyama Univ., Japan

pp. 119

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Constructing an Edge-Route Guaranteed Optimal Fault-Tolerant Routing for Biconnected Graphs (Abstract)

Yupin Luo, Tsinghua University

Shiyuan Yang, Tsinghua University

Dongcheng Hu, Tsinghua University

pp. 123

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Session 3A: Synthesis for Testability

An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan (Abstract)

T. Inoue, Nara Inst. of Sci. & Technol., Japan

T. Masuzawa, Nara Inst. of Sci. & Technol., Japan

H. Youra, Nara Inst. of Sci. & Technol., Japan

H. Fujiwara, Nara Inst. of Sci. & Technol., Japan

pp. 130

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Waveform Polynomial Manipulation Using Bdds (Abstract)

Zhuxing Zhao, Inst. of Comput. Technol., Acad. Sinica, Beijing, China

Zhongcheng Li, Inst. of Comput. Technol., Acad. Sinica, Beijing, China

Yinghua Min, Inst. of Comput. Technol., Acad. Sinica, Beijing, China

pp. 136

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Easily Testable Data Path Allocation Using Input/Output Registers (Abstract)

Li-Ren Huang, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Jing-Yang Jou, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Sy-Yen Kuo, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Wen-Bin Liao, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

pp. 142

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AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth (Abstract)

Harry Hengster, Albert-Ludwigs-University

Rolf Drechsler, Albert-Ludwigs-University

Bernd Becker, Albert-Ludwigs-University

Stefan Eckrich, Johann Wolfgang Goethe-University

Tonja Pfeiffer, Johann Wolfgang Goethe-University

pp. 148

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Minimal Delay Test Sets for Unate Gate Networks (Abstract)

U. Sparmann, University of Saarland

H. Mueller, University of Saarland

S.M. Reddy, University of Iowa

pp. 155

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Session 3B: IDDQ and Fault Modeling

Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults (Abstract)

Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Jing-Jou Tang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

pp. 165

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Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits (Abstract)

Toshimasa Kuchii, The University of Tokushima

Masaki Hashizume, The University of Tokushima

Takeomi Tamesada, The University of Tokushima

pp. 171

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An Efficient Compact Test Generator for IDDQ Testing (Abstract)

Hisashi Kondo, Kawasaki Steel Corp.

Kwang-Ting Cheng, University of California, Santa Barbara

pp. 177

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Realistic Linked Memory Cell Array Faults (Abstract)

A.J. van de Goor, Delft University of Technology

G.N. Gaydadjiev, Delft University of Technology

pp. 183

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On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family (Abstract)

Teruhiko Yamada, Meiji University

Tsuyoshi Sasaki, Meiji University

pp. 189

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"Built-In Self Test for Analog and Mixed-Signal Designs" (PDF)

Kwang-Ting (Tim) Cheng

pp. 197

Session 4A: Built-In Self-Test

An Efficient PRPG Strategy By Utilizing Essential Faults (Abstract)

Li-Ren Huang, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Jing-Yang Jou, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Sy-Yen Kuo, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

pp. 199

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DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique (Abstract)

Saman Adham, Northern Telecom

Sanjay Gupta, Northern Telecom

pp. 205

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A MISR Computation Algorithm for Fast Signature Simulation (Abstract)

Bin-Hong Lin, National Tsing Hua University

Shao-Hui Shieh, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 213

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BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design (Abstract)

Kowen Lai

Christos A. Papachristou

pp. 219

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Session 4B: Circuit and System-Level Diagnostics

Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach (Abstract)

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 226

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Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation (Abstract)

Tao Wei, Hong Kong Polytechnic University

Mike W.T. Wong, Hong Kong Polytechnic University

Y.S. Lee, Hong Kong Polytechnic University

pp. 232

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A Practical Implementation Of Dynamic Testing Of An Ad Converter (Abstract)

Yuan Tzu Ting, Chung Sun Inst. of Sci. & Technol., Lung-Tan, Taiwan

Li Wei Chao, Chung Sun Inst. of Sci. & Technol., Lung-Tan, Taiwan

Wei Chung Chao, Chung Sun Inst. of Sci. & Technol., Lung-Tan, Taiwan

pp. 238

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Comparison Diagnosis in Large Multiprocessor Systems (Abstract)

Christopher P. Fuhrman, Swiss Federal Institute of Technology

Henri J. Nussbaumer, Swiss Federal Institute of Technology

pp. 244

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Session 5A: Industrial Applications

Lessons Learned from Practical Applications of BIST/B-S Technology (Abstract)

Najmi Jarwala, Lucent Technologies Bell Labs Innovations

Paul W. Rutkowski, Lucent Technologies Bell Labs Innovations

Shianling Wu, Lucent Technologies Bell Labs Innovations

Chi Yau, Lucent Technologies Bell Labs Innovations

pp. 251

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Yield Improvement by Test Error Cancellation (Abstract)

Jwu E. Chen

pp. 258

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A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology (Abstract)

V.C. Alves, COPPE, Univ. Fed. do Rio de Janeiro, Brazil

A.R. Antunes, COPPE, Univ. Fed. do Rio de Janeiro, Brazil

M. Marzouki, COPPE, Univ. Fed. do Rio de Janeiro, Brazil

pp. 263

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A New Model with Time Constraints for Conformance Testing of Communication Protocols (Abstract)

Daisuke Teratani, Osaka University

Yoshiaki Kakuda, Osaka University

Tohru Kikuno, Osaka University

pp. 269

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Session 5B: Practical Issues

Test Generation Of Analog Switched-Current Circuits (Abstract)

Cheng-Ping Wang, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA

Chin-Long Wey, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA

pp. 276

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Thermal Monitoring Of Safety-Critical Integrated Systems (Abstract)

V. Székely, Technical University of Budapest

M. Rencz, Technical University of Budapest

J.M Karam, TIMA

M. Lubaszewski, TIMA

B. Courtois, TIMA

pp. 282

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A New Scheme For The Fault Diagnosis Of Multiprocessor Systems (Abstract)

Xiaofan Yang, Comput. Inst., Chongqing Univ., China

Tinghuai Chen, Comput. Inst., Chongqing Univ., China

Zehan Cao, Comput. Inst., Chongqing Univ., China

Zhongshi He, Comput. Inst., Chongqing Univ., China

Hongqing Cao, Comput. Inst., Chongqing Univ., China

pp. 289

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On-Line Testing In Digital Neural Networks (Abstract)

S. Demidenko, Singapore Polytech., Singapore

V. Piuri, Singapore Polytech., Singapore

pp. 295

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Author Index (PDF)

pp. 301