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Fifth Asian Test Symposium (ATS'96)
On Design of Fail-Safe Cellular Arrays
Hsinchu, TAIWAN
November 20-November 22
ISBN: 0-8186-7478-4
Naotake Kamiura, Himeji Institute of Technology
Yutaka Hata, Himeji Institute of Technology
Kazuharu Yamato, Himeji Institute of Technology
In this paper, we discuss the design of a fail-safe cellular array composed of switch cells. First, we show the design method using a binary decision diagram. Next, we assume stuck-at faults of switch cells to be fault models and discuss the fail-safe property for our array. For all the single faults and part of the multiple faults, our array keeps the fail-safe property. Next, for our arrays realizing randomly generated functions, we derive the ratio of the number of double faults that never break the fail-safe property to the total number of double faults. Finally, in order to demonstrate the advantages of our array, we compare our array with other arrays.
Index Terms:
fail-safe logic system, cellular array, Binary Decision Diagram and switch cell
Citation:
Naotake Kamiura, Yutaka Hata, Kazuharu Yamato, "On Design of Fail-Safe Cellular Arrays," ats, pp.107, Fifth Asian Test Symposium (ATS'96), 1996
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