[Front cover]

doi:10.1109/ASYNC.2012.33

A
ASYNC
2012
2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

Lyngby Denmark

May 07-May 09

ISBN: 978-0-7695-4688-9

Table of Contents

Papers

[Front cover] (PDF)

pp. C1

ABSTRACT

PDF

[Title page i] (PDF)

pp. i

ABSTRACT

PDF

[Title page iii] (PDF)

pp. iii

pp. iv-iv

Table of contents (PDF)

pp. v-vii

ABSTRACT

PDF

Message from the Chairs - ASYNC 2012 (PDF)

pp. viii-ix

ABSTRACT

PDF

Symposium Committee (PDF)

pp. x-x

ABSTRACT

PDF

Technical Program Committee (PDF)

pp. xi-xi

ABSTRACT

PDF

Additional reviewers - ASYNC 2012 (PDF)

pp. xii-xii

ABSTRACT

PDF

Steering Committee (PDF)

pp. xiii-xiii

ABSTRACT

PDF

Keynotes (PDF)

pp. xiv-xvi

ABSTRACT

PDF

Statistical Analysis and Optimization of Asynchronous Digital Circuits (Abstract)

pp. 1-8

ABSTRACT

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Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior (Abstract)

pp. 9-16

ABSTRACT

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Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation (Abstract)

pp. 17-24

ABSTRACT

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A Digital Neurosynaptic Core Using Event-Driven QDI Circuits (Abstract)

pp. 25-32

ABSTRACT

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A Low Power Asynchronous GPS Baseband Processor (Abstract)

pp. 33-40

ABSTRACT

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High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism (Abstract)

pp. 41-48

ABSTRACT

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An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery (Abstract)

pp. 49-56

ABSTRACT

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A Fast Hierarchical Approach to Resource Sharing in Pipelined Asynchronous Systems (Abstract)

pp. 57-64

ABSTRACT

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Uncle - An RTL Approach to Asynchronous Design (Abstract)

pp. 65-72

ABSTRACT

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A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits (Abstract)

pp. 73-80

ABSTRACT

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Ultra Low Power Booth Multiplier Using Asynchronous Logic (Abstract)

pp. 81-88

ABSTRACT

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An Asynchronous Floating-Point Multiplier (Abstract)

pp. 89-96

ABSTRACT

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An Asynchronous Divider Implementation (Abstract)

pp. 97-104

ABSTRACT

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Tiempo Asynchronous Circuits System Verilog Modeling Language (Abstract)

pp. 105-112

ABSTRACT

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Introduction to Octasic Asynchronous Processor Technology (Abstract)

pp. 113-117

ABSTRACT

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DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems (Abstract)

pp. 118-125

ABSTRACT

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Performance Analysis of GALS Datalink Based on Pausible Clocking (Abstract)

pp. 126-133

ABSTRACT

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PID (Partial Inversion Data): An M-of-N Level-Encoded Transition Signaling Protocol for Asynchronous Global Communication (Abstract)

pp. 134-141

ABSTRACT

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Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects (Abstract)

pp. 142-149

ABSTRACT

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Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes (Abstract)

pp. 150-157

ABSTRACT

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Author index (PDF)

pp. 158-158

ABSTRACT

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IEEE Computer Society Technical & Conference Activities Board [Publisher's information] (PDF)

pp. 160-160

ABSTRACT

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