CSDL - Proceedings A

Committees (PDF)

pp. x

Additional Reviewers (PDF)

pp. xi

Signaling with Conserved Quantities: Two Realizations in CMOS and Superconducting Flux Quantum Logic (PDF)

Invited Talk 1

pp. xiii

Invited Talk 2

Thinking Outside the Box in Geometry and Art (PDF)

pp. xiv

Invited Talk 3

Too Many Robots, Too Little Time (PDF)

pp. xv

Invited Talk 4

Statistical Variations Are Inevitable - Can We Cope With Them? (PDF)

pp. xvi

Session 1: High-Speed Links and Signaling

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link (Abstract)

Rostislav Reuven Dobkin, Israel Institute of Technology, Haifa

Yevgeny Perelman, Israel Institute of Technology, Haifa

Tuvia Liran, Israel Institute of Technology, Haifa

Ran Ginosar, Israel Institute of Technology, Haifa

Avinoam Kolodny, Israel Institute of Technology, Haifa

pp. 3-14

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Notes On Pulse Signaling (Abstract)

Jo Ebergen, Sun Microsystems Laboratories, Menlo Park

Steve Furber, Sun Microsystems Laboratories, Menlo Park

Arash Saifhashemi, Sun Microsystems Laboratories, Menlo Park

pp. 15-24

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A Jitter Attenuating Timing Chain (Abstract)

Suwen Yang, SUN Microsystems, and NSERC

Mark R. Greenstreet, SUN Microsystems, and NSERC

Jihong Ren, Intel

pp. 25-38

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Session 2: Asynchronous Applications

The Vortex: A Superscalar Asynchronous Processor (Abstract)

Andrew Lines, Fulcrum Microsystems, Calabasas, CA, USA

pp. 39-48

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Design of a High-Speed Asynchronous Turbo Decoder (Abstract)

Pankaj Golani, University of Southern California, Los Angeles

Georgios D. Dimou, University of Southern California, Los Angeles

Mallika Prakash, University of Southern California, Los Angeles

Peter A. Beerel, University of Southern California, Los Angeles

pp. 49-59

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Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus (Abstract)

Andrew M. Scott, Intel Corporation, Austin, TX

Mark E. Schuelein, Intel Corporation, Austin, TX

Marly Roncken, Intel Corporation, Austin, TX

Jin-Jer Hwan, Intel Corporation, Austin, TX

John Bainbridge, Silistix Ltd., Manchester, UK

John R. Mawer, Silistix Ltd., Manchester, UK

David L. Jackson, Silistix Ltd., Manchester, UK

Andrew Bardsley, Silistix Ltd., Manchester, UK

pp. 60-72

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Session 3: Verification

Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip (Abstract)

Gwen Salaun, INRIA Rhone-Alpes / VASY, Montbonnot, France

Wendelin Serwe, INRIA Rhone-Alpes / VASY, Montbonnot, France

Yvain Thonnart, CEA/Leti - MINATEC, Grenoble, France

Pascal Vivet, CEA/Leti - MINATEC, Grenoble, France

pp. 73-82

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Gate-level modelling and verification of asynchronous circuits using CSPM and FDR (Abstract)

Mark B. Josephs, London South Bank University, UK

pp. 83-94

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Session 4: Novel Circuits

The Design of a Genetic Muller C-Element (Abstract)

Nam-Phuong D. Nguyen, University of Utah

Hiroyuki Kuwahara, University of Utah

Chris J. Myers, University of Utah

James P. Keener, University of Utah

pp. 95-104

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Delay/Phase Regeneration Circuits (Abstract)

Crescenzo D?Alessandro, Newcastle University, UK

Andrey Mokhov, Newcastle University, UK

Alex Bystrov, Newcastle University, UK

Alex Yakovlev, Newcastle University, UK

pp. 105-116

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Session 5: Synthesis

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis (Abstract)

Tiberiu Chelcea, Carnegie Mellon University

Girish Venkataramani, Carnegie Mellon University

Seth C. Goldstein, Carnegie Mellon University

pp. 117-128

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A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers (Abstract)

Melinda Y. Agyekum, Columbia University

Steven M. Nowick, Columbia University

pp. 129-142

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Session 6: Test and Measurement

A Configurable Asynchronous Pseudorandom Bit Sequence Generator (Abstract)

Alex Chow, Sun Microsystems, Menlo Park, CA

William S. Coates, Sun Microsystems, Menlo Park, CA

David Hopkins, Sun Microsystems, Menlo Park, CA

pp. 143-152

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On-chip samplers for test and debug of asynchronous circuits (Abstract)

Frankie Liu, Sun Microsystems Laboratories, Menlo Park, CA

Ron Ho, Sun Microsystems Laboratories, Menlo Park, CA

Robert Drost, Sun Microsystems Laboratories, Menlo Park, CA

Scott Fairbanks, Sun Microsystems Laboratories, Menlo Park, CA

pp. 153-162

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A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability (Abstract)

Nikolaos Minas, Newcastle University, UK

David Kinniment, Newcastle University, UK

Keith Heron, Newcastle University, UK

Gordon Russell, Newcastle University, UK

pp. 163-174

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Session 7: Interfaces

Demystifying Data-Driven and Pausible Clocking Schemes (Abstract)

Robert Mullins, University of Cambridge, UK

Simon Moore, University of Cambridge, UK

pp. 175-185

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Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication (Abstract)

Amitava Mitra, Intel Corporation, Bangalore, India

William F. McLaughlin, Columbia University

Steven M. Nowick, Columbia University

pp. 186-195

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Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces (Abstract)

Wade L. Williams, Advanced Micro Devices

Philip E. Madrid, Advanced Micro Devices

Scott C. Johnson, Advanced Micro Devices

pp. 196-204

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Author Index

Author Index (PDF)

pp. 205