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12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)
Grenoble, France
March 13-March 15
ISBN: 0-7695-2498-2
Table of Contents
Introduction
Cover
Invited Talk 1
Session 1: Interfacing and Synchronization
David Kinniment, Newcastle University, UK
Keith Heron, Newcastle University, UK
Gordon Russell, Newcastle University, UK
pp. 2-11
Jo Ebergen, Sun Microsystems Laboratories, USA
Alex Chow, Sun Microsystems Laboratories, USA
Bill Coates, Sun Microsystems Laboratories, USA
Justin Schauer, Sun Microsystems Laboratories, USA
David Hopkins, Sun Microsystems Laboratories, USA
pp. 23-33
Session 2: Fault-Tolerance and Testing
Session 3: Novel Architectures and Design Practices
L. Necchi, Politecnico di Torino, Italy
L. Lavagno, Politecnico di Torino, Italy
D. Pandini, STMicroelectronics Agrate (MI), Italy
L. Vanzago, STMicroelectronics Agrate (MI), Italy
pp. 78-85
D. Caucheteux, CEA-Grenoble, LETI-DCIS, Cedex, France
E. Beigne, CEA-Grenoble, LETI-DCIS, Cedex, France
E. Crochon, CEA-Grenoble, LETI-DCIS, Cedex, France
M. Renaudin, TIMA Laboratory, CIS Group, Cedex, France
pp. 86-97
Invited Talk 2
Session 4: Interconnect and Communcations
Mark R. Greenstreet, University of British Columbia
Jihong Ren, University of British Columbia
pp. 98-106
Crescenzo D?Alessandro, University of Newcastle upon Tyne, UK
Delong Shang, University of Newcastle upon Tyne, UK
Alex Bystrov, University of Newcastle upon Tyne, UK
Alex Yakovlev, University of Newcastle upon Tyne, UK
Oleg Maevsky, Intel Labs, Moscow, RU
pp. 107-116
Rostislav (Reuven) Dobkin, Israel Institute of Technology, Haifa, Israel
Ran Ginosar, Israel Institute of Technology, Haifa, Israel
Avinoam Kolodny, Israel Institute of Technology, Haifa, Israel
pp. 117-127
Session 5: Synthesis
W. B. Toms, University of Manchester, UK
D. A. Edwards, University of Manchester, UK
A Bardsley, Silistix Ltd., UK
pp. 138-149
Invited Talk 3
Ferdinand Peper, National Institute of Information and Communications Technology, Japan
pp. xiv
Session 6: Design and Architectures for GALS
Frank K. Gurkaynak, Integrated Systems Laboratory, CH-8092 ETH Zurich
Stephan Oetiker, Integrated Systems Laboratory, CH-8092 ETH Zurich
Hubert Kaeslin, Integrated Systems Laboratory, CH-8092 ETH Zurich
Norbert Felber, Integrated Systems Laboratory, CH-8092 ETH Zurich
Wolfgang Fichtner, Integrated Systems Laboratory, CH-8092 ETH Zurich
pp. 150-159
Joycee Mekie, Indian Institute of Technology, Bombay
Supratik Chakraborty, Indian Institute of Technology, Bombay
D.K. Sharma, Indian Institute of Technology, Bombay
Girish Venkataramani, Carnegie Mellon University
P. S. Thiagarajan, National University of Singapore
pp. 160-171
Session 7: Slack Matching
Peter A. Beerel, University of Southern California
Nam-Hoon Kim, University of Southern California
Andrew Lines, Fulcrum Microsystems, Inc., Calabasas Hills, CA
Mike Davies, Fulcrum Microsystems, Inc., Calabasas Hills, CA
pp. 184-194
Piyush Prakash, California Institute of Technology
Alain J. Martin, California Institute of Technology
pp. 195-204
Author Index
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