CSDL - Proceedings A

12th IEEE International Symposium on Asynchronous Circuits and Systems - Title Page (PDF)

pp. i-iii

12th IEEE International Symposium on Asynchronous Circuits and Systems - Copyright (PDF)

pp. iv

Introduction

Message from the Chairs (PDF)

pp. viii

Committees (PDF)

pp. x

Invited Talk 1

Asynchronous Design: An Enabler for Flexible Microelectronics (PDF)

Nobuo Karaki, Seiko Epson Corp., Japan.

pp. xii

Session 1: Interfacing and Synchronization

Measuring Deep Metastability (Abstract)

David Kinniment, Newcastle University, UK

Keith Heron, Newcastle University, UK

Gordon Russell, Newcastle University, UK

pp. 2-11

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A Level-Crossing Flash Asynchronous Analog-to-Digital Converter (Abstract)

Filipp Akopyan, Cornell University

Rajit Manohar, Cornell University

Alyssa B. Apsel, Cornell University

pp. 12-22

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An Asynchronous High-Throughput Control Circuit For Proximity Communication (Abstract)

Jo Ebergen, Sun Microsystems Laboratories, USA

Alex Chow, Sun Microsystems Laboratories, USA

Bill Coates, Sun Microsystems Laboratories, USA

Justin Schauer, Sun Microsystems Laboratories, USA

David Hopkins, Sun Microsystems Laboratories, USA

pp. 23-33

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Session 2: Fault-Tolerance and Testing

Self-Healing Asynchronous Arrays (Abstract)

Song Peng, Cornell University

Rajit Manohar, Cornell University

pp. 34-45

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Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines (Abstract)

Gennette Gill, UNC Chapel Hill

Ankur Agiwal, UNC Chapel Hill

Montek Singh, UNC Chapel Hill

Feng Shi, Yale University

Yiorgos Makris, Yale University

pp. 46-56

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A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines (Abstract)

Feng Shi, Yale University

Yiorgos Makris, Yale University

pp. 57-67

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A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations (Abstract)

Session 3: Novel Architectures and Design Practices

Masashi Imai, University of Tokyo

Takashi Nanya, University of Tokyo

pp. 68-77

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An ultra-low energy asynchronous processor for Wireless Sensor Networks (Abstract)

L. Necchi, Politecnico di Torino, Italy

L. Lavagno, Politecnico di Torino, Italy

D. Pandini, STMicroelectronics Agrate (MI), Italy

L. Vanzago, STMicroelectronics Agrate (MI), Italy

pp. 78-85

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AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation (Abstract)

D. Caucheteux, CEA-Grenoble, LETI-DCIS, Cedex, France

E. Beigne, CEA-Grenoble, LETI-DCIS, Cedex, France

E. Crochon, CEA-Grenoble, LETI-DCIS, Cedex, France

M. Renaudin, TIMA Laboratory, CIS Group, Cedex, France

pp. 86-97

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ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture (PDF)

Invited Talk 2

Jean-Pierre Schoellkopf, STMicroelectronics, France

pp. xiii

Session 4: Interconnect and Communcations

Surfing Interconnect (Abstract)

Mark R. Greenstreet, University of British Columbia

Jihong Ren, University of British Columbia

pp. 98-106

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Multiple-Rail Phase-Encoding for NoC (Abstract)

Crescenzo D?Alessandro, University of Newcastle upon Tyne, UK

Delong Shang, University of Newcastle upon Tyne, UK

Alex Bystrov, University of Newcastle upon Tyne, UK

Alex Yakovlev, University of Newcastle upon Tyne, UK

Oleg Maevsky, Intel Labs, Moscow, RU

pp. 107-116

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Fast Asynchronous Shift Register for Bit-Serial Communication (Abstract)

Rostislav (Reuven) Dobkin, Israel Institute of Technology, Haifa, Israel

Ran Ginosar, Israel Institute of Technology, Haifa, Israel

Avinoam Kolodny, Israel Institute of Technology, Haifa, Israel

pp. 117-127

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Session 5: Synthesis

Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks (Abstract)

Cheoljoo Jeong, Columbia University, NY

Steven M. Nowick, Columbia University, NY

pp. 128-137

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Synthesising Heterogeneously Encoded Systems (Abstract)

W. B. Toms, University of Manchester, UK

D. A. Edwards, University of Manchester, UK

A Bardsley, Silistix Ltd., UK

pp. 138-149

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Invited Talk 3

Asynchronous Architectures for Nanometer Scales (PDF)

Ferdinand Peper, National Institute of Information and Communications Technology, Japan

pp. xiv

Session 6: Design and Architectures for GALS

GALS at ETH Zurich: Success or Failure (Abstract)

Frank K. Gurkaynak, Integrated Systems Laboratory, CH-8092 ETH Zurich

Stephan Oetiker, Integrated Systems Laboratory, CH-8092 ETH Zurich

Hubert Kaeslin, Integrated Systems Laboratory, CH-8092 ETH Zurich

Norbert Felber, Integrated Systems Laboratory, CH-8092 ETH Zurich

Wolfgang Fichtner, Integrated Systems Laboratory, CH-8092 ETH Zurich

pp. 150-159

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Interface Design for Rationally Clocked GALS Systems (Abstract)

Joycee Mekie, Indian Institute of Technology, Bombay

Supratik Chakraborty, Indian Institute of Technology, Bombay

D.K. Sharma, Indian Institute of Technology, Bombay

Girish Venkataramani, Carnegie Mellon University

P. S. Thiagarajan, National University of Singapore

pp. 160-171

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Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture (Abstract)

E. Beigne, CEA-LETI, France

P. Vivet, CEA-LETI, France

pp. 172-183

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Session 7: Slack Matching

Slack Matching Asynchronous Designs (Abstract)

Peter A. Beerel, University of Southern California

Nam-Hoon Kim, University of Southern California

Andrew Lines, Fulcrum Microsystems, Inc., Calabasas Hills, CA

Mike Davies, Fulcrum Microsystems, Inc., Calabasas Hills, CA

pp. 184-194

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Slack Matching Quasi Delay-Insensitive Circuits (Abstract)

Piyush Prakash, California Institute of Technology

Alain J. Martin, California Institute of Technology

pp. 195-204

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Author Index

Author Index (PDF)

pp. 205