Message from the Chairs

Additional reviewers (PDF)

pp. x

Papers

Steering Committee (PDF)

pp. x

Technical Program Committee (PDF)

pp. ix

Symposium Committee (PDF)

pp. ix

Invited Talk 1

Deep Pipelines vs. Risk and Power Walls (PDF)

Bob Colwell, R.E. Collwell and Associates, Inc.

pp. xi

Session 1: Circuit Techniques

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Energy Efficient Surfing (Abstract)

Suwen Yang, University of British Columbia

Brian D. Winters, University of British Columbia

Mark R. Greenstreet, University of British Columbia

pp. 2-11

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GasP Control for Domino Circuits (Abstract)

Jo Ebergen, Sun Microsystems Laboratories

Jonathan Gainsley, Sun Microsystems Laboratories

Jon Lexau, Sun Microsystems Laboratories

Ivan Sutherland, Sun Microsystems Laboratories

pp. 12-22

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Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic (Abstract)

Tin Wai Kwan, Carleton University

Maitham Shams, Carleton University

pp. 23-32

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Session 2: On-Chip Networks

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A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip (Abstract)

Tobias Bjerregaard, Technical University of Denmark

Jens Spars?, Technical University of Denmark

pp. 34-43

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An Asynchronous Router for Multiple Service Levels Networks on Chip (Abstract)

Dobkin (Reuven) Rostislav, Technion-Israel Institute of Technology

Victoria Vishnyakov, Technion-Israel Institute of Technology

Eyal Friedman, Technion-Israel Institute of Technology

Ran Ginosar, Technion-Israel Institute of Technology

pp. 44-53

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An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework (Abstract)

E. Beign?, CEA-LETI

F. Clermidy, CEA-LETI

P. Vivet, CEA-LETI

A. Clouard, STMicroelectronics

M. Renaudin, TIMA Laboratory

pp. 54-63

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Session 3: Clocking and Synchronization

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Joep Kessels, Philips Technology Incubator

pp. 66-75

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Request-Driven GALS Technique for Wireless Communication System (Abstract)

Miloš Krstić, IHP

Eckhard Grass, IHP

Christian Stahl, Humboldt Universit?

pp. 76-85

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Self-Timed Circuitry for Global Clocking (Abstract)

Scott Fairbanks, Cambridge University

Simon Moore, Cambridge University

pp. 86-96

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Invited Talk 2

Proximity Communication and Time (PDF)

Robert Drost, Sun Microsystems Laboratories

Ivan Sutherland, Sun Microsystems Laboratories

pp. xii

Session 4: Design Analysis

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Modeling and Verifying Circuits Using Generalized Relative Timing (Abstract)

Sanjit A. Seshia, Carnegie Mellon University

Randal E. Bryant, Carnegie Mellon University

Kenneth S. Stevens, Intel Strategic CAD Labs

pp. 98-108

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Controlling Event Spacing in Self-Timed Rings (Abstract)

V. Zebilis, ICS-FORTH

C. P. Sotiriou, ICS-FORTH

pp. 109-115

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Delay Insensitive Encoding and Power Analysis: A Balancing Act (Abstract)

Konrad J. Kulikowski, Boston University

Ming Su, Boston University

Alexander Smirnov, Boston University

Alexander Taubin, Boston University

Mark G. Karpovsky, Boston University

Daniel MacDonald, Boston University

pp. 116-125

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Session 5: Design Implementations

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A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier (Abstract)

Justin Hensley, University of North Carolina

Anselmo Lastra, University of North Carolina

Montek Singh, University of North Carolina

pp. 128-137

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Continuous-Time Digital Signal Processors (Abstract)

Y. W. Li, Columbia University

K. L. Shepard, Columbia University

Y. P. Tsividis, Columbia University

pp. 138-143

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BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor (Abstract)

Virantha N. Ekanayake, Cornell University

Clinton Kelly, IV, Cornell University

Rajit Manohar, Cornell University

pp. 144-154

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Session 6: Test and Reliability

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SEU-Tolerant QDI Circuits (Abstract)

Wonjin Jang, California Institute of Technology

Alain Martin, California Institute of Technology

pp. 156-165

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A Multiplexor Based Test Method for Self-Timed Circuits (Abstract)

Frank te Beest, Philips Technology Incubator

Ad Peeters, Philips Technology Incubator

pp. 166-175

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Invited Tutorial

New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems (PDF)

Phillip Restle, IBM T.J. Watson

Ken Shepard, Columbia University

pp. xiii

Session 7: Encoding and Synthesis

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High Level Synthesis of Timed Asynchronous Circuits (Abstract)

Tomohiro Yoneda, National Institute of Informatics

Atsushi Matsumoto, Tokyo Institute of Technology

Manabu Kato, Tokyo Institute of Technology

Chris Myers, University of Utah

pp. 178-189

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Behavior and Synthesis of Two-Input Gate Asynchronous Circuits (Abstract)

Nikolai Starodoubtsev, Tokyo University of Social Welfare

Sergei Bystrov, Russian Academy of Science

pp. 190-200

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A Unified Coding Framework for Delay-Insensitivity (Abstract)

Frédéric Worm, Ecole Polytechnique Fédérale de Lausanne

Patrick Thiran, Ecole Polytechnique Fédérale de Lausanne

Paolo Ienne, Ecole Polytechnique Fédérale de Lausanne

pp. 201-211

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Author Index

Author Index (PDF)

pp. 212