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11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'05)
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
New York City, New York, USA
March 14-March 16
ISBN: 0-7695-2305-6
| ASCII Text | x | ||
| E. Beign?, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, "An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework," 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, pp. 54-63, 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'05), 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/ASYNC.2005.10, author = {E. Beign? and F. Clermidy and P. Vivet and A. Clouard and M. Renaudin}, title = {An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework}, journal ={2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems}, volume = {0}, year = {2005}, issn = {1522-8681}, pages = {54-63}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2005.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems TI - An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework SN - 1522-8681 SP54 EP63 A1 - E. Beign?, A1 - F. Clermidy, A1 - P. Vivet, A1 - A. Clouard, A1 - M. Renaudin, PY - 2005 KW - null VL - 0 JA - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2005.10
The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new Asynchronous Network-On-Chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a Delay Insensitive asynchronous Network-on-Chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and Transaction-Level-Modeling. Preliminary simulation results show that the Asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13um CMOS technology.
Citation:
E. Beign?, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, "An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework," async, pp.54-63, 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'05), 2005
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