CSDL - Proceedings A

Symposium Committee (PDF)

pp. x-xii

Keynote I

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Synchronous Latency Insensitive Design (PDF)

Christer Svensson, Link?ping University

pp. 3

Session I: Design and Test

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A Fast and Energy-Efficient Stack (Abstract)

Jo Ebergen, Sun Microsystems Laboratories

Daniel Finchelstein, Sun Microsystems Laboratories

Russell Kao, Sun Microsystems Laboratories

Jon Lexau, Sun Microsystems Laboratories

David Hopkins, Sun Microsystems Laboratories

pp. 7-16

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Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis (Abstract)

John Teifel, Cornell University

Rajit Manohar, Cornell University

pp. 17-27

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General Testers for Asynchronous Circuits (Abstract)

Radu Negulescu, McGill University

pp. 28-38

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Session II: Timing

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Analog Micropipeline Rings for High Precision Timing (Abstract)

Scott Fairbanks, Cambridge University

Simon Moore, Cambridge University

pp. 41-50

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Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit (Abstract)

Jo Ebergen, Sun Microsystems Laboratories

Jonathan Gainsley, Sun Microsystems Laboratories

Paul Cunningham, Sun Microsystems Laboratories

pp. 51-61

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Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model (Abstract)

Masashi Imai, University of Tokyo

Metehan Özcan, University of Tokyo

Takashi Nanya, University of Tokyo

pp. 62-71

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Session III: Asynchronous Designs I

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Non-Uniform Access Asynchronous Register Files (Abstract)

David Fang, Cornell University

Rajit Manohar, Cornell University

pp. 75-85

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Phase Alignment Using Asynchronous State Machines (Abstract)

Alireza S Kaviani, Xilinx Research Labs

pp. 86-94

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High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells (Abstract)

Marcos Ferretti, University of Southern California

Recep O. Ozdag, University of Southern California

Peter A. Beerel, University of Southern California

pp. 95-105

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Keynote II

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Contacting Biological Cells with Electronic Circuits (PDF)

Martin Jenkner, Infineon Technologies

pp. 109

Session IV: Synthesis and Verification

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Bolstering Faith in GasP Circuits through Formal Verification (Abstract)

Xiaohua Kong, McGill University

Radu Negulescu, McGill University

pp. 113-124

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A General Purpose Behavioural Asynchronous Synthesis System (Abstract)

pp. 125-134

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Synthesis of Speed Independent Circuits Based on Decomposition (Abstract)

Tomohiro Yoneda, National Institute of Informatics

Hiroomi Onda, Tokyo Institute of Technology

Chris Myers, University of Utah

pp. 135-145

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Session V: Synchronization

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Handshake Protocols for De-Synchronization (Abstract)

I. Blunno, Politecnico di Torino

J. Cortadella, Universidad Politècnica de Catalunya

A. Kondratyev, Cadence Berkeley Labs

L. Lavagno, Politecnico di Torino and Cadence Berkeley Labs

K. Lwin, Cadence Berkeley Labs

C. Sotiriou, ICS-FORTH

pp. 149-158

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Hiding Synchronization Delays in a GALS Processor Microarchitecture (Abstract)

Greg Semeraro, Rochester Institute of Technology

David H. Albonesi, University of Rochester

Grigorios Magklis, University of Rochester

Michael L. Scott, University of Rochester

Steven G. Dropsho, University of Rochester

Sandhya Dwarkadas, University of Rochester

pp. 159-169

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Data Synchronization Issues in GALS SoCs (Abstract)

Rostislav (Reuven) Dobkin, Technion-Israel Institute of Technology

Ran Ginosar, Technion-Israel Institute of Technology

Christos P. Sotiriou, ICS-FORTH

pp. 170-180

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Keynote III

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Bringing Handshake Technology to the Open Market (PDF)

Ad Peeters, Handshake Solutions

pp. 183

A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates (Abstract)

Session VI: Asynchronous Design II

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Recep O. Ozdag, University of Southern California

Peter A. Beerel, University of Southern California

pp. 187-197

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Asynchronous FIR Filters: Towards a New Digital Processing Chain (Abstract)

F. Aeschlimann, TIMA Laboratory

E. Allier, TIMA Laboratory

L. Fesquet, TIMA Laboratory

M. Renaudin, TIMA Laboratory

pp. 198-206

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An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm (Abstract)

A. Efthymiou, University of Manchester

W. Suntiamorntut, University of Manchester

J. Garside, University of Manchester

L. E. M. Brackenbury, University of Manchester

pp. 207-215

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Session VII: High Speed and Pulse Logic

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High-Speed Reduced Stack Dual Lock Circuits (Abstract)

Nisrine Saadallah, McGill University

Xiaohua Kong, McGill University

Radu Negulescu, McGill University

pp. 219-228

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An Eight-Bit Divider Implemented in Asynchronous Pulse Logic (Abstract)

Mika Nyström, California Institute of Technology

Elaine Ou, California Institute of Technology

Alain J. Martin, California Institute of Technology

pp. 229-239

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Long Wires and Asynchronous Control (Abstract)

Ron Ho, Sun Microsystems Research Laboratories

Jon Gainsley, Sun Microsystems Research Laboratories

Robert Drost, Sun Microsystems Research Laboratories

pp. 240-249

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Author Index

Author Index (PDF)

pp. 251